https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115687
--- Comment #5 from palmer at gcc dot gnu.org --- (In reply to Andrew Pinski from comment #3) > (In reply to Andrew Pinski from comment #2) > > There is some code in cse.cc which does handle this. > > See > > https://gcc.gnu.org/onlinedocs/gccint/Misc.html#index- > > TARGET_005fCONST_005fANCHOR also. > > MIPS, aarch64 and rs6000 all define TARGET_CONST_ANCHOR (well MIPS sets > targetm.const_anchor depending on if it is mips16/micromips or mips32/64). Oh, thanks, I didn't know about that. It looks like just adding diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9bba5da016e..6080298c36c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -12019,6 +12019,9 @@ riscv_c_mode_for_floating_type (enum tree_index ti) #undef TARGET_C_MODE_FOR_FLOATING_TYPE #define TARGET_C_MODE_FOR_FLOATING_TYPE riscv_c_mode_for_floating_type +#undef TARGET_CONST_ANCHOR +#define TARGET_CONST_ANCHOR 0x4000 + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" isn't enough for us here, but it seems like we should have something along those lines. 2d7c73ee5ea ("AArch64: Enable TARGET_CONST_ANCHOR") has a test case, so hopefully it's not that tricky to get something that exposes the issue on RISC-V as well...
