https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115950
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Keywords| |aarch64-sve
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
Last reconfirmed| |2024-07-16
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.
Failed to match this instruction:
(set (reg:DI 104 [ _4 ])
(plus:DI (zero_extend:DI (unspec:SI [
(reg:VNx16BI 106)
(const_int 0 [0])
(reg:VNx16BI 106)
] UNSPEC_CNTP))
(reg:DI 105)))
We have:
;; Increment an SImode register by the number of set bits in a predicate
;; using modular arithmetic. See aarch64_sve_cntp for a description of
;; the operands.
(define_insn_and_rewrite "*aarch64_incsi<mode>_cntp"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI
(unspec:SI [(match_operand 3)
(const_int SVE_KNOWN_PTRUE)
(match_operand:PRED_ALL 2 "register_operand" "Upa")]
UNSPEC_CNTP)
(match_operand:SI 1 "register_operand" "0")))]
"TARGET_SVE"
"incp\t%x0, %2.<Vetype>"
"&& !CONSTANT_P (operands[3])"
{
operands[3] = CONSTM1_RTX (<MODE>mode);
}
)
But not the zero_extend pattern.
Should not be hard to add. maybe sign_extend is also needed.
Due to this:
```
using s64 = int64_t;
s64 foo3(s64 x, svbool_t pg)
{
return x+(signed char)svcntp_b8(pg, pg);
}
```
Which gives:
Failed to match this instruction:
(set (reg:DI 106 [ _6 ])
(plus:DI (sign_extend:DI (subreg:QI (unspec:SI [
(reg:VNx16BI 109)
(const_int 0 [0])
(reg:VNx16BI 109)
] UNSPEC_CNTP) 0))
(reg:DI 108)))
