https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116041
--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The trunk branch has been updated by Andrew Pinski <pins...@gcc.gnu.org>: https://gcc.gnu.org/g:7223c64745530db102a160d5a1db4c2c8d2b9fe1 commit r15-2840-g7223c64745530db102a160d5a1db4c2c8d2b9fe1 Author: Andrew Pinski <quic_apin...@quicinc.com> Date: Tue Aug 6 16:00:02 2024 -0700 aarch64/testsuite: Fix if-compare_2.c for removing vcond{,u,eq} patterns [PR116041] For bar1 and bar2, we currently is expecting to use the bsl instruction but with slightly different register allocation inside the loop (which happens after the removal of the vcond{,u,eq} patterns), we get the bit instruction. The pattern that outputs bsl instruction will output bit and bif too depending register allocation. So let's check for bsl, bit or bif instructions instead of just bsl instruction. Tested on aarch64 both with an unmodified compiler and one which has the patch to disable these optabs. gcc/testsuite/ChangeLog: PR testsuite/116041 * gcc.target/aarch64/if-compare_2.c: Support bit and bif for both bar1 and bar2; add comment on why too. Signed-off-by: Andrew Pinski <quic_apin...@quicinc.com>
