https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116662
--- Comment #4 from Jonathan Wakely <redi at gcc dot gnu.org> --- (In reply to Levi Zim from comment #0) > But this value is 32 for riscv64, which seems wrong to me because IIRC > many riscv64 cpus have cacheline of size 64. If this is only true for "man riscv64 cpus" and not all, then maybe 32 is an appropriate default. If you know you're using hardware with 64-byte cachelines, then you can compile your code with: --param l1-cache-line-size=64 or leave the cache line size unchanged, and use: --param destructive-interference-size=64 But see -Winterference-size in the GCC manual.
