[Bug target/117205] New: RISC-V: Redundant vector memcpy loop

[craig.blackmore at embecosm dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117205

            Bug ID: 117205
           Summary: RISC-V: Redundant vector memcpy loop
           Product: gcc
           Version: 15.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: craig.blackmore at embecosm dot com
  Target Milestone: ---

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111720#c30 allowed a redundant
straight-line vector memcpy in pr111720-0.c to be eliminated.

I modified pr111720-0.c to need a vector memcpy loop and the memcpy does not
get eliminated.

New test:

#include "riscv_vector.h"

vuint8m1_t test () {
  uint8_t arr[256] = {
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
    1, 2, 7, 1, 3, 4, 5, 3,
    1, 0, 1, 2, 4, 4, 9, 9,
  };

  return __riscv_vle8_v_u8m1(arr, 32);
}

GCC (commit 54b3f8e7bc0b572c1966aece20a0ac942aa4af97) with -O3 -march=rv64gcv
-mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl:

test:
        addi    sp,sp,-256
        lui     a5,%hi(.LANCHOR0)
        addi    a5,a5,%lo(.LANCHOR0)
        mv      a2,sp
        li      a3,256
.L2:
        vsetvli a4,a3,e8,m8,ta,ma
        vle8.v  v8,0(a5)
        sub     a3,a3,a4
        add     a5,a5,a4
        vse8.v  v8,0(a2)
        add     a2,a2,a4
        bne     a3,zero,.L2
        li      a5,32
        vsetvli zero,a5,e8,m1,ta,ma
        vle8.v  v8,0(sp)
        addi    sp,sp,256
        jr      ra

LLVM (commit 46df20ab63ee8c14c5d4eef07e2a7cccd466c064) with -O3 -march=rv64gcv
-mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl:

test:
.Lpcrel_hi0:
        auipc   a0, %pcrel_hi(.L__const.test.arr)
        addi    a0, a0, %pcrel_lo(.Lpcrel_hi0)
        li      a1, 32
        vsetvli zero, a1, e8, m1, ta, ma
        vle8.v  v8, (a0)
        ret