https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117914
Bug ID: 117914
Summary: [reload][avr] In function '__objc_add_class_to_hash
class-i.c:2162:1: error: insn does not satisfy its
constraints:
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: other
Assignee: unassigned at gcc dot gnu.org
Reporter: gjl at gcc dot gnu.org
Target Milestone: ---
Created attachment 59791
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59791&action=edit
precompiled C test case
$ avr-gcc-15 class-i.c -S -Os -mmcu=avrtiny -w -da
class-i.c: In function '__objc_add_class_to_hash':
class-i.c:2162:1: error: insn does not satisfy its constraints:
2162 | }
| ^
(insn 46 153 154 8 (set (reg:SI 24 r24 [orig:52 _10 ] [52])
(ashift:SI (reg:SI 30 r30)
(const_int 16 [0x10]))) "class-i.c":2153:141 494 {ashlsi3}
(nil))
during RTL pass: postreload
class-i.c:2162:1: internal compiler error: in extract_constrain_insn, at
recog.cc:2770
0x7f2ed6359d8f __libc_start_call_main
../sysdeps/nptl/libc_start_call_main.h:58
reg30:SI is obviously invalid as a register, because the last GPR is reg31.QI,
and the maximal mode which reg30 can hold is HImode.
In .asmcons we have:
(insn 46 44 47 8 (set (reg:SI 52 [ _10 ])
(ashift:SI (subreg:SI (reg:HI 50 [ class_number.6_8 ]) 0)
(const_int 16 [0x10]))) "class-i.c":2153:141 494 {ashlsi3}
(nil))
which in .postreload has been turned into:
(insn 46 153 154 8 (set (reg:SI 24 r24 [orig:52 _10 ] [52])
(ashift:SI (reg:SI 30 r30)
(const_int 16 [0x10]))) "class-i.c":2153:141 494 {ashlsi3}
(nil))
So paradoxical subreg subreg:SI (reg:HI 50 [ class_number.6_8 ]) 0) is turned
into an invalid hard register.
FYI, the ICE goes away with -mlra.
