[Bug target/112268] AVR-GCC generates suboptimal code for bit shifts

[gjl at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112268

Georg-Johann Lay <gjl at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |15.0
         Depends on|                            |117726, 84211, 107957
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #1 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
With PR84211, PR107957, PR117726 in place, the generated code with v15 is:

uint8_t extract22 (uint32_t val) { return val >> 22; }
uint8_t extract23 (uint32_t val) { return val >> 23; }
uint8_t extract24 (uint32_t val) { return val >> 24; }
uint8_t extract25 (uint32_t val) { return val >> 25; }
uint8_t extract26 (uint32_t val) { return val >> 26; }
uint8_t extract27 (uint32_t val) { return val >> 27; }
uint8_t extract28 (uint32_t val) { return val >> 28; }
uint8_t extract29 (uint32_t val) { return val >> 29; }
uint8_t extract30 (uint32_t val) { return val >> 30; }
uint8_t extract31 (uint32_t val) { return val >> 31; }

extract22:
    ldi r18,6    ;  23  [c=20 l=5]  *lshrhi3_const/3
    1:  
    lsr r25
    ror r24
    dec r18 
    brne 1b 
    ret

extract23:
    lsl r24      ;  23  [c=20 l=5]  *lshrhi3_const/1
    mov r24,r25
    rol r24
    sbc r25,r25
    neg r25
    ret

extract24:
    mov r24,r25  ;  21  [c=4 l=1]  movqi_insn/0
    ret

extract25:
    mov r24,r25  ;  23  [c=4 l=1]  movqi_insn/0
    lsr r24      ;  24  [c=4 l=1]  *lshrqi3/1
    ret

extract26:
    mov r24,r25  ;  23  [c=4 l=1]  movqi_insn/0
    lsr r24      ;  24  [c=8 l=2]  *lshrqi3/1
    lsr r24 
    ret

extract27:
    mov r24,r25  ;  23  [c=4 l=1]  movqi_insn/0
    lsr r24      ;  24  [c=12 l=3]  *lshrqi3/3
    lsr r24 
    lsr r24 
    ret

extract28:
    mov r24,r25  ;  23  [c=4 l=1]  movqi_insn/0
    swap r24     ;  24  [c=16 l=2]  *lshrqi3/3
    andi r24,0x0f
    ret

extract29:
    mov r24,r25  ;  23  [c=4 l=1]  movqi_insn/0
    swap r24     ;  24  [c=20 l=3]  *lshrqi3/3
    lsr r24
    andi r24,0x7
    ret

extract30:
    ldi r24,1<<2     ;  23  [c=16 l=4]  *lshrqi3/2
    mul r24,r25
    mov r24,r1
    clr __zero_reg__
    ret

extract31:
    bst r25,7    ;  18  [c=4 l=3]  *extzvqi
    clr r24
    bld r24,0
    ret


Referenced Bugs:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84211
[Bug 84211] [avr] Perform a post-reload register optimization pass
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107957
[Bug 107957] [AVR] Missed optimization in access to upper-half of a variable
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117726
[Bug 117726] [avr] better optimize multi-byte shifts