https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117974
Bug ID: 117974
Summary: RISC-V: VSETVL hoisting across branch
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: vineetg at gcc dot gnu.org
CC: jeffreyalaw at gmail dot com, juzhe.zhong at rivai dot ai,
rdapp at gcc dot gnu.org
Target Milestone: ---
This came out of some tinkering with "C" testcase in
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117733
float g(float q[], int N){
float dqnorm = 0.0;
#pragma GCC unroll 4
for (int i=0; i < N; i++) {
dqnorm = dqnorm + q[i] * q[i];
}
return dqnorm;
}
-march=rv64gcv_zvl256b -Ofast -mrvv-vector-bits=zvl
g:
ble a1,zero,.L4
vsetivli zero,4,e32,m1,ta,ma
vmv.v.i v1,0
.L3:
vsetvli a5,a1,e32,m1,tu,ma
vle32.v v2,0(a0)
sub a1,a1,a5
slli a4,a5,2
add a0,a0,a4
vfmacc.vv v1,v2,v2
vsetvli a5,a1,e32,m1,tu,ma <---
slli a4,a5,2
beq a1,zero,.L12
vle32.v v2,0(a0)
...
...
The VSETVL for VLE32 is hoisted before the BEQ. It would have been better to
keep this closer to VLE, after the branch for zero, to potentially avoid
setting VL=0 which might be expensive on some uarches.
