[Bug target/117990] [15 regression] RISC-V: Miscompile at -O3 zvl 256 since r15-4746-g30435cc2610

[pan2.li at intel dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117990

--- Comment #4 from Li Pan <pan2.li at intel dot com> ---
Another example to reproduce this.

   1   │ #define STEP 10
   2   │
   3   │ char d[225];
   4   │ int e[STEP];
   5   │
   6   │ int main() {
   7   │   for (long h = 0; h < STEP; ++h)
   8   │     d[h * STEP] = 9; // 0, 10, 20, 30, 40, 50, 60, 70, 80, 90
   9   │
  10   │   for (int h = 3; h < STEP; h += 1)
  11   │     e[h] = d[h * STEP]; // 30, 40, 50, 60, 70, 80, 90
  12   │                         //  3,  4,  5,  6,  7,  8,  9
  13   │
  14   │   if (e[5] != 9) {
  15   │     return 123;
  16   │   } else {
  17   │     return 0;
  18   │   }
  19   │ }

QEMU_CPU=rv64,vlen=256,rvv_ta_all_1s=true,rvv_ma_all_1s=true,v=true,vext_spec=v1.0
~/bin/qemu/bin/qemu-riscv64 test.elf

FAIL:
  - ../__RV64/bin/riscv64-unknown-elf-gcc test.c -march=rv64gcvb_zvl256b -O2
-mrvv-vector-bits=zvl -o test.elf


PASS:
  - ../__RV64/bin/riscv64-unknown-elf-gcc test.c -march=rv64gcvb_zvl256b -O1
-mrvv-vector-bits=zvl -o test.elf
  -