[Bug target/118057] New: RISC-V: Can't vectorize load and store with zvl128b

[sh.chiang04 at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118057

            Bug ID: 118057
           Summary: RISC-V: Can't vectorize load and store with zvl128b
           Product: gcc
           Version: 15.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: sh.chiang04 at gmail dot com
  Target Milestone: ---

I found a test in the mcp() function of Lmbench. The clang can generate vlse
and vsse instructions.

Clang ASM (https://godbolt.org/z/jzsK6bsGa):

Lmbench source:
https://github.com/intel/lmbench/blob/master/src/bw_mem.c#L267

compile option:
  -O3 -march=rv64gcv_zvl128b

test:
typedef struct _state {
 int *buf;
 int *buf2;
} state_t;

void vload_store (void *src, int *last)
{
  state_t *state = (state_t *) src;
  register int *p = state->buf;
  register int *dst = state->buf2;
  while (p <= last) {
    dst[0] = p[0]; dst[4] = p[4];
    dst[8] = p[8]; dst[12] = p[12]; 
    dst[16] = p[16]; dst[20] = p[20]; dst[24] = p[24];
    p += 128;
    dst += 128;
  }
}

GCC ASM:
vload_store:
        ld      a5,0(a0)
        bgtu    a5,a1,.L5
        ld      a4,8(a0)
.L3:
        lw      a3,0(a5)
        addi    a5,a5,512
        addi    a4,a4,512
        sw      a3,-512(a4)
        lw      a3,-496(a5)
        sw      a3,-496(a4)
        lw      a3,-480(a5)
        sw      a3,-480(a4)
        lw      a3,-464(a5)
        sw      a3,-464(a4)
        lw      a3,-448(a5)
        sw      a3,-448(a4)
        lw      a3,-432(a5)
        sw      a3,-432(a4)
        lw      a3,-416(a5)
        sw      a3,-416(a4)
        bgeu    a1,a5,.L3
.L5:
        ret