https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118776
--- Comment #14 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jakub Jelinek <ja...@gcc.gnu.org>: https://gcc.gnu.org/g:64d8ea056a5c339700118a412dea1c44a57acf55 commit r15-7437-g64d8ea056a5c339700118a412dea1c44a57acf55 Author: Jakub Jelinek <ja...@redhat.com> Date: Sat Feb 8 08:54:31 2025 +0100 i386: Fix ICE with conditional QI/HI vector maxmin [PR118776] The following testcase ICEs starting with GCC 12 since r12-4526 although the bug has been introduced already in r12-2751. The problem was in the addition of cond_<code><mode> define_expand which uses nonimmediate_operand predicates for both maxmin operands for all VI1248_AVX512VLBW modes. It works fine with VI48_AVX512VL modes because the <code><mode>3_mask VI48_AVX512VL define_expand uses ix86_fixup_binary_operands_no_copy and the *avx512f_<code><mode>3<mask_name> VI48_AVX512VL define_insn uses % in constraint and !(MEM_P && MEM_P) check in condition (and <code><mode>3 define_expand with VI124_256_AVX512F_AVX512BW iterator does that too), but eventhough the 8-bit and 16-bit element maxmin is commutative too, the <mask_codefor><code><mode>3<mask_name> define_insn with VI12_AVX512VL iterator didn't use % in constraint to make it commutative. So, e.g. cond_umaxv32qi define_expand allowed nonimmediate_operand for both umax operands, but used gen_umaxv32qi_mask which wasn't commutative and only allowed nonimmediate_operand for the second operand. The following patch fixes it by keeping the <code><mode>3 VI124_256_AVX512F_AVX512BW define_expand as is (it does ix86_fixup_binary_operands_no_copy) but extending the <code><mode>3_mask define_expand from VI48_AVX512VL to VI1248_AVX512VLBW which keeps the current modes with their ISA conditions and adds the VI12_AVX512VL modes under additional TARGET_AVX512BW condition, and turning the actual define_insn into an * prefixed name (which it was before just for the non-masked case) and having the same commutative operand handling as in other define_insns. 2025-02-08 Jakub Jelinek <ja...@redhat.com> PR target/118776 * config/i386/sse.md (<code><mode>3_mask): Use VI1248_AVX512VLBW iterator rather than VI48_AVX512VL. (<mask_codefor><code><mode>3<mask_name>): Rename to ... (*avx512bw_<code><mode>3<mask_name>): ... this. Use nonimmediate_operand rather than register_operand predicate and %v rather than v constraint for operand 1 and adjust condition to reject MEMs in both operand 1 and 2. * gcc.target/i386/pr118776.c: New test.
