[Bug target/118832] RISC-V: internal compiler error: could not split insn, with V+Zbb enabled

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118832

--- Comment #4 from Robin Dapp <rdapp at gcc dot gnu.org> ---
>From a cursory look the following shifts might also be vulnerable:
(riscv-v.cc:1528)

              else
                {
                  /* { 1, 3, 2, 6, ... }.  */
                  rtx tmp2 = gen_reg_rtx (new_mode);
                  base2 = gen_int_mode (rtx_to_poly_int64 (base2), new_smode);
                  expand_vec_series (tmp2, base2,
                                     gen_int_mode (step2, new_smode));
                  rtx shifted_tmp2 = expand_simple_binop (
                    new_mode, ASHIFT, tmp2,
                    gen_int_mode (builder.inner_bits_size (), Pmode), NULL_RTX,
                    false, OPTAB_DIRECT);


(riscv-v.cc:1546)

          else
            {
              rtx vid = gen_reg_rtx (mode);
              expand_vec_series (vid, const0_rtx, const1_rtx);
              /* Transform into { 0, 0, 1, 1, 2, 2, ... }.  */
              rtx shifted_vid
                = expand_simple_binop (mode, LSHIFTRT, vid, const1_rtx,
                                       NULL_RTX, false, OPTAB_DIRECT);