https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120362
--- Comment #6 from Robin Dapp <rdapp at gcc dot gnu.org> ---
(In reply to Kito Cheng from comment #5)
> Oh, vsetvli/vill issue should only appeared for whole reg move not whole reg
> load store
On the Banana Pi I get a SIGILL for
int
main() {
asm volatile ("lui a5, 0xdd\n\t"
"add a5, a5, 904\n\t"
"vl1re32.v v1,(a5)\n\t"
:
:
:);
return 0;
}
but a SIGSEGV (which is OK) for
int
main() {
asm volatile ("lui a5, 0xdd\n\t"
"add a5, a5, 904\n\t"
"vsetivli zero,8,e32,m1,ta,ma\n\t"
"vl1re32.v v1,(a5)\n\t"
:
:
:);
return 0;
}
So looks like we also need a vtype for the loads and stores?
