https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71921
--- Comment #22 from Andrew Pinski <pinskia at gcc dot gnu.org> --- (In reply to Andrew Pinski from comment #21) > Trying 22 -> 27: > 22: r118:V4SF=r113:V4SF<const_vector > REG_EQUAL r113:V4SF<const_vector > 27: r121:V4SF=~r118:V4SF&r113:V4SF > REG_DEAD r118:V4SF > REG_DEAD r113:V4SF > Failed to match this instruction: > (set (reg:V4SF 121) > (and:V4SF (not:V4SF (lt:V4SF (reg:V4SF 113 [ MEM <const vector(4) float> > [(const float *)input_12(D) + ivtmp.21_83 * 1] ]) > (const_vector:V4SF [ > (const_double:SF 0.0 [0x0.0p+0]) repeated x4 > ]))) > (reg:V4SF 113 [ MEM <const vector(4) float> [(const float > *)input_12(D) + ivtmp.21_83 * 1] ]))) > > > Since we know the vector is 0, this should be changed to: > (if_then_else (lt r113 0) 0 r113) > > Which then can be recongized ... Or the backend could recognize the and not form ...
