[Bug target/121118] New: ICE when constructing a fixed-length SVE predicate

[rsandifo at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121118

            Bug ID: 121118
           Summary: ICE when constructing a fixed-length SVE predicate
           Product: gcc
           Version: 16.0
            Status: UNCONFIRMED
          Keywords: aarch64-sve, ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: rsandifo at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64*-*-*

[https://godbolt.org/z/fYffh9bn8]

Compiling:

typedef __SVBool_t fixed_bool __attribute__((arm_sve_vector_bits(256)));

fixed_bool foo() {
  union { unsigned int i; fixed_bool pg; } u = { 0x02aaaaaa };
  return u.pg;
}

with -O2 -march=armv8-a+sve -msve-vector-bits=256 leads to:

<source>: In function 'foo':
<source>:6:1: error: unrecognizable insn:
    6 | }
      | ^
(insn 10 9 14 2 (set (reg:VNx16BI 101 [ <retval> ])
        (unspec:VNx16BI [
                (reg:VNx16BI 103)
                (reg:VNx8BI 105)
                (const_vector:VNx16BI [
                        (const_int 0 [0]) repeated x32
                    ])
            ] UNSPEC_TRN1_CONV)) "<source>":5:11 discrim 1 -1
     (expr_list:REG_EQUAL (const_vector:VNx16BI [
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0])
                (const_int 1 [0x1])
                (const_int 0 [0]) repeated x6
            ])
        (nil)))
during RTL pass: vregs
<source>:6:1: internal compiler error: in extract_insn, at recog.cc:2882
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
See <https://gcc.gnu.org/bugs/> for instructions.

We're trying to use a TRN1 of a zero and a WHILELO, but the WHILELO input has
the wrong mode: VNx8BI instead of VNx16BI.

I think this is the cause of
https://github.com/pytorch/pytorch/issues/157626#issuecomment-3054480096 , but
I haven't yet confirmed.