[Bug target/121027] [14 Regression] ICE with BF16 and SVE at -O2 -msve-vector-bits=256

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121027

--- Comment #8 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-14 branch has been updated by Richard Sandiford
<rsand...@gcc.gnu.org>:

https://gcc.gnu.org/g:86ecf3e5832a3fd1fc0ecfbb03e91ca8e6aa806e

commit r14-11912-g86ecf3e5832a3fd1fc0ecfbb03e91ca8e6aa806e
Author: Richard Sandiford <richard.sandif...@arm.com>
Date:   Sat Jul 26 18:38:48 2025 +0100

    aarch64: Fix general permutes of svbfloat16_ts [PR121027]

    Testing gcc.target/aarch64/sve/permute_2.c without the associated GCC
    patch triggered an unrecognisable insn ICE for the svbfloat16_t tests.
    This was because the implementation of general two-vector permutes
    requires two TBLs and an ORR, with the ORR being represented as an
    unspec for floating-point modes.  The associated pattern did not
    cover VNx8BF.

    gcc/
            PR target/121027
            * config/aarch64/iterators.md (SVE_I): Move further up file.
            (SVE_F): New mode iterator.
            (SVE_ALL): Redefine in terms of SVE_I and SVE_F.
            * config/aarch64/aarch64-sve.md (*<LOGICALF:optab><mode>3): Extend
            to all SVE_F.

    gcc/testsuite/
            PR target/121027
            * gcc.target/aarch64/sve/permute_5.c: New test.

    (cherry picked from commit 4fd473f66faf5bd95c84fe5c0fa41be735a7c09f)