https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121198
--- Comment #3 from Stefan Schulze Frielinghaus <stefansf at gcc dot gnu.org>
---
During constraint processing we have
7: {r45:SI=asm_operands;clobber cc:CC;}
REG_DEAD r47:HI
REG_UNUSED cc:CC
Alt 0: (0) ={r22} (1) {r22}
Final costs after insn 7 (freq=1000)
...
Creating newreg=49 from oldreg=45, assigning class SIMPLE_LD_REGS to r49
This is not satisfiable since for an SImode value we need four registers and
r24/r25 are not in SIMPLE_LD_REGS. The register class is determined via
REGNO_REG_CLASS(regno) which returns the smallest class containing REGNO which
is in this case SIMPLE_LD_REGS. This, does not guarantee that a register pair
fits.
Since we already select via a filter the hard register, we could set the class
to ALL_REGS. Could you give the following a try:
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 83f8fda3b52..18298e14586 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -2551,7 +2551,7 @@ process_alt_operands (int only_alternative)
{
int regno = decode_hard_reg_constraint (p);
gcc_assert (regno >= 0);
- cl = REGNO_REG_CLASS (regno);
+ cl = ALL_REGS;
CLEAR_HARD_REG_SET (hard_reg_constraint);
SET_HARD_REG_BIT (hard_reg_constraint, regno);
cl_filter = &hard_reg_constraint;
It works for me in a cross compiler.
