https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121485
Bug ID: 121485
Summary: RISC-V Zvkned vector-scalar intrinsics use wrong EMUL
(m1 for m2/m4/m8 variants of intrinsics)
Product: gcc
Version: 15.1.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: jussi.kivilinna at iki dot fi
Target Milestone: ---
I noticed issue with '__riscv_vaesz_vs_u32m1_u32m4' intrinsic with GCC
(riscv64) where intrinsic generated assembly with element group of 1 (m1)
instead of expected m4.
Following example:
#include <riscv_vector.h>
vuint32m4_t test_riscv_vaesz_vs_u32m1_u32m4(vuint32m4_t a, vuint32m1_t b, int
vl)
{
// Expecting vsetvli with "m4", gcc generates "m1"...
return __riscv_vaesz_vs_u32m1_u32m4(a, b, vl);
}
Results in:
test_riscv_vaesz_vs_u32m1_u32m4:
vsetvli zero,a0,e32,m1,ta,ma
vaesz.vs v8,v12
ret
Expected assembly is (as generated by clang):
test_riscv_vaesz_vs_u32m1_u32m4:
vsetvli zero, a0, e32, m4, ta, ma
vaesz.vs v8, v12
ret
Same issue is with m2/m4/m8 vector-scalar variants of
vaesz/vaesem/vaesef/vaesdm/vaesdf intrinsics. Tested with Godbolt riscv64 gcc
15.1.0 and gcc trunk: https://godbolt.org/z/4jGo74M3o