https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114673
Christoph Müllner <cmuellner at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |INVALID
Status|ASSIGNED |RESOLVED
--- Comment #4 from Christoph Müllner <cmuellner at gcc dot gnu.org> ---
Andreas is right, the "L" constraint is part of the TARGET_SFB_ALU
functionality.
My statement that it was introduced as part of the initial RISC-V port was
incorrect. Instead, it was introduced in this commit:
commit 4f4753914455ad186f7c1f994743abfcb05a7dc9
Author: Andrew Waterman <[email protected]>
Date: Tue Apr 30 16:45:36 2019 -0700
RISC-V: Short-forward-branch opt for SiFive 7 series cores.
If I remember correctly, I was working on a similar (shifted) constraint when I
reported this and found the implementation of "L" odd. I assumed that "L" was
meant to work in inline assembly for LUI (still a reasonable conclusion from
the description "A U-type 20-bit signed immediate."). However, that's not the
case as Andreas has pointed out.
Not having an inline assembly constraint for LUI is fine for me.
I'll close this as invalid.
