[Bug target/122970] RISC-V: Wrong code generated with -mrvv-vector-bits=zvl for SLP vectorization

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122970

--- Comment #1 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Good find, this is another bug in the interleaving pattern where we reinterpret
the series as if it had a larger type.  Testing a patch.