https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123278
--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <[email protected]>: https://gcc.gnu.org/g:14449749559587968b96c1e54e1fd4a4a0d9ace0 commit r16-6369-g14449749559587968b96c1e54e1fd4a4a0d9ace0 Author: Jeff Law <[email protected]> Date: Tue Dec 23 12:34:44 2025 -0700 [RISC-V][PR target/123278] Handle BF/HF modes in Andes 45 series pipeline description So a standard run-of-the-mill case where we're testing modes to determine what reservation to use in a pipeline model and modes were missing (BF/HF in this case). This adds the BF/HF cases to the fp_alu_s, fpu_mul_s and fpu_mac_s units for the Andes 45 series. It may ultimately be the case that even lower latencies are available for these ops, but that's something folks with a better understanding of the Andes 45 series uarch would need to tackle. Tested on riscv32-elf and riscv64-elf. Given the nature of the change and the fact that I expect to be out of the office most of the next few days, I'm going to go ahead and push without waiting for pre-commit CI. There's minimal risk. PR target/123278 gcc/ * config/riscv/andes-45-series.md (andes_45_fpu_alu_s): Handle BF/HF modes too. (andes_45_fpu_mul_s, andes_45_fpu_mac_s): Likewise. gcc/testsuite/ * gcc.target/riscv/pr123278.c: New test.
