https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123308
Bug ID: 123308
Summary: Recent ifcvt's change causes RISC-V regressions
Product: gcc
Version: 16.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: law at gcc dot gnu.org
Target Milestone: ---
This patch:
commit 9e61a171244110a45a87bb010704f2f9d4030181
Author: Andrew Pinski <[email protected]>
Date: Mon Dec 22 17:58:35 2025 -0800
ifcvt: Fix noce_try_cond_zero_arith after get_base_reg change [PR123267]
A few fixes are needed after the change to get_base_reg of
r16-6333-gac64ceb33bf05b. First we need to use the correct target mode
of the operand, this means if we are doing a subreg of QI mode, using
QImode for the conditional move.
Second we also need to use the original operands instead of the ones
removing the subreg still.
Pushed as obvious after a bootstrap/test on x86_64-linux-gnu.
Caused regressions on RISC-V:
Tests that now fail, but worked before (1 tests):
unix/-march=rv64gc_zba_zbb_zbs_zicond: gcc: gcc.target/riscv/zicond_ifcvt_opt.c
-O2 scan-assembler-times czero\\.eqz 41
If we look at something like test_ShiftLeft_eqz before the patch it generated:
czero.eqz a3,a2,a3
sll a0,a1,a3
ret
After the patch:
mv a0,a1
beq a3,zero,.L171
sll a0,a1,a2
.L171:
ret
The czero form is clearly better.
