https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94892
--- Comment #8 from Jeffrey A. Law <law at gcc dot gnu.org> --- Note for anyone looking at this. I did a bit of a hack to simplify_relational_operation_1 which recognizes when we do an equality test of a sign bit splat against zero is just a ge/lt test. That works well and clearly improves the RISC-V code generated. The problem is it regresses on AVR. I didn't see any other targets with regressions when I threw that hack into my tester. THe AVR failure: avr-sim: gcc: gcc.target/avr/pr109907.c scan-assembler-not shr The code is clearly worse after my change for AVR. The problem is the AVR has limited forms of conditionals which don't include ge/lt instrutions. THe AVR port has special patterns that recognize the form generated for pr109907.c and if rewritten into a ge/lt test against zero we end up with an extra copy and clearly worse code. Conceptually shifting the value left so that the sign bit goes into C, then clearing the destination and finally inserting C into destination seems like a good sequence for AVR. It'd probably work well except that the AVR claims to support non-destructive ops which leads to problems getting good code out of the register allocator as we end up with an extraneous copy. Just wanted to get that noted for the record. I'm currently planning to address this for RISC-V with couple define_insns to capture the relevant cases.
