https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125148
--- Comment #11 from Tamar Christina <tnfchris at gcc dot gnu.org> --- The change in g:210d06502f22964c7214586c54f8eb54a6965bfd added aarch64_emit_load_store_through_mode which converts known elementwise predicated SVE loads into Adv. SIMD loads. this changed the VL1 byte load into a LDR QI load. It then takes a paradoxical subreg of this (subreg:VNx16QI (reg:QI 111) 0) which is where the issues start. It's relying on the implicit zero-ing behavior of the top bits of the LDR and so declares it doesn't are about the top bits. But the LDR may not stay an LDR. in this case the value was immediately stored before the load. so eventually cse removes the load and transforms it into (set (reg:QI 111) (const_int 1)) which is valid, but when allocated to the FPR side generates a movi, because the immediate move code assumes that the scalar is accessed in the mode it is created in. So a paradoxical subreg must not be used until we are sure the top bits are zero. Testing a patch...
