https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125389
--- Comment #3 from Surya Kumari Jangala <jskumari at gcc dot gnu.org> --- The approach used in this bugzilla is preferable as it is extensible. For Power processors that will be available in the future, it will be very easy to specify the predicates (such as altivec, vsx, dmf (a feature in the next power processor) etc). If we are able to specify multiple gating predicates in the rs6000-builtins.def file, we can easily specify [future,vsx], [future,altivec], [future,dmf] etc. With the approach used in https://gcc.gnu.org/pipermail/gcc-patches/2025-December/703405.html , every new feature combination requires: - adding new enums, - extending structures, - updating tables, - and touching multiple places again. And this will become very messy.
