https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125780
Bug ID: 125780
Summary: [avr][17 Regression] ICE: unable to find a register to
spill: in lra_split_hard_reg_for, at
lra-assigns.cc:1885
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: gjl at gcc dot gnu.org
Target Milestone: ---
Created attachment 64734
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=64734&action=edit
spill.c: C test case
typedef __UINT32_TYPE__ uint32_t;
uint32_t xdiv (uint32_t a, uint32_t b)
{
register int r18 __asm("18") = 0x1122;
__asm volatile ("seh ; %0" : "+r" (r18), "+r" (a));
uint32_t c = a / b;
__asm volatile ("clh ; %0" : "+r" (r18), "+r" (c));
return c;
}
$ avr-gcc -mmcu=attiny40 -Os -S -v
spill.c: In function 'xdiv':
spill.c:10:1: error: unable to find a register to spill
10 | }
| ^
spill.c:10:1: error: this is the insn:
(insn 10 29 24 2 (parallel [
(set (reg:SI 55 [orig:47 c_7 ] [47])
(udiv:SI (reg:SI 56 [orig:46 a ] [46])
(reg:SI 57)))
(set (reg:SI 58 [48])
(umod:SI (reg:SI 56 [orig:46 a ] [46])
(reg:SI 57)))
(clobber (reg:HI 52))
(clobber (reg:HI 53))
]) "spill.c":7:14 621 {udivmodsi4}
(expr_list:REG_UNUSED (reg:SI 58 [48])
(expr_list:REG_DEAD (reg:SI 57)
(expr_list:REG_DEAD (reg:SI 56 [orig:46 a ] [46])
(expr_list:REG_UNUSED (reg:HI 53)
(expr_list:REG_UNUSED (reg:HI 52)
(nil)))))))
during RTL pass: reload
spill.c:10:1: internal compiler error: in lra_split_hard_reg_for, at
lra-assigns.cc:1885
This ICE is related to hard-reg constraints as introduced in
https://gcc.gnu.org/r17-891.
Different to other HRC problems, this one is not fixed by
0001-ira-Treat-hard-register-constraints-similarly-as-sin.patch from
https://gcc.gnu.org/pipermail/gcc-patches/2026-May/718682.html
This is the insn from avr.md:
(define_insn_and_split "udivmodsi4"
[(set (match_operand:SI 0 "register_operand" "={r18}")
(udiv:SI (match_operand:SI 1 "register_operand" "{r22}")
(match_operand:SI 2 "register_operand" "{r18}")))
(set (match_operand:SI 3 "register_operand" "={r22}")
(umod:SI (match_dup 1)
(match_dup 2)))
(clobber (match_scratch:HI 4 "=x"))
(clobber (match_scratch:HI 5 "=z"))]
""
"#"
"&& reload_completed"
[(scratch)]
{ DONE_ADD_CCC })
R18..R19 are callee-saved. The remaining involved regs (R20..R25, x=R26..R27,
z=R30..R31) are call-clobbered. What RA could to is to spill R18..R19 to
R28..R29 when to frame pointer is needed (R28..R29 is FP), or spill to a stack
slot. xdiv receives argument a in R22..R25 and arg b on the stack.
Target: avr
Configured with: ../../source/gcc-master/configure --target=avr --disable-nls
--with-dwarf2 --with-gnu-as --with-gnu-ld --with-long-double=64
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 17.0.0 20260613 (experimental) (GCC)
