https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125794
Drea Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Last reconfirmed| |2026-06-14
Ever confirmed|0 |1
Summary|aarch64: incorrect SVE |[17 Regression] aarch64:
|assembly for loop |incorrect SVE assembly for
| |loop
Target Milestone|--- |17.0
Status|UNCONFIRMED |NEW
--- Comment #1 from Drea Pinski <pinskia at gcc dot gnu.org> ---
The RTL is correct, just that does not correspond to that constant forming.
(insn:TI 30 20 29 (set (reg:V4SI 63 v31 [126])
(const_vector:V4SI [
(const_int 0 [0])
(const_int 1 [0x1])
(const_int 0 [0]) repeated x2
])) "/app/example.cpp":11:8 discrim 33792 1384
{*aarch64_simd_movv4si}
(expr_list:REG_EQUIV (const_vector:V4SI [
(const_int 0 [0])
(const_int 1 [0x1])
(const_int 0 [0]) repeated x2
])
(nil)))
