https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122665
--- Comment #9 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The releases/gcc-16 branch has been updated by jeevitha <[email protected]>: https://gcc.gnu.org/g:b0a9b346b0545bc3d23449478892e2cb755ef0ef commit r16-9147-gb0a9b346b0545bc3d23449478892e2cb755ef0ef Author: Jeevitha <[email protected]> Date: Mon Jun 22 15:02:12 2026 -0500 rs6000: Fix [su]mul<mode>3_highpart patterns to use RTL codes [PR122665] The existing smul<mode>3_highpart and umul<mode>3_highpart patterns incorrectly defined the high-part multiply by shifting both operands right by 32 before multiplication. This does not match the semantics of the instructions vmulhs<wd> and vmulhu<wd>, which perform a widened multiplication and return the high part of the result. This patch replaces the incorrect shift-based patterns with the proper smul_highpart and umul_highpart RTL codes, and updates the operand predicate from vsx_register_operand to altivec_register_operand, since these instructions only accept Altivec registers. 2026-05-13 Jeevitha Palanisamy <[email protected]> gcc/ PR target/122665 * config/rs6000/vsx.md (smul<mode>3_highpart, umul<mode>3_highpart): Replace shift-based patterns with smul_highpart and umul_highpart RTL codes and use altivec_register_operand. (cherry picked from commit 3c6318c5ecbccbbfa76e90f97c69e6aa74bf7c5d)
