https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126585
Bug ID: 126585
Summary: [13/14/15/16/17 Regression] ICE in vect_get_loop_mask
with SVE
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Keywords: aarch64-sve, ice-on-valid-code
Severity: normal
Priority: P3
Component: tree-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: ktkachov at gcc dot gnu.org
Target Milestone: ---
Target: aarch64
/* ICE in vect_get_loop_mask (tree-vect-loop.cc:10639) from
vectorizable_condition (tree-vect-stmts.cc:12567).
gcc -O3 -march=armv8.2-a+sve -msve-vector-bits=256 -S pr.c
vectorizable_condition decides to apply a loop mask by looking the scalar
condition up in scalar_cond_masked_set with a hardcoded ncopies of 1, but
then fetches the mask with the node's own vec_num. Here the char
.MASK_STORE for b[] records the key with nvectors == 1 while the COND node
has vec_num == 2, and no rgroup with nvectors == 2 was ever recorded, so
masks->rgc_vec[1] is a safe_grow_cleared hole with type == NULL_TREE. */
void f (int *restrict p, signed char *restrict b, int *restrict o, int n)
{
for (int i = 0; i < n; i++)
{
signed char t0 = p[2*i] >> 3;
signed char t1 = p[2*i+1] >> 3;
if (t0 > 0) b[i] = 1;
o[2*i] = (t0 > 0 ? t0 : 3) * p[2*i];
o[2*i+1] = (t1 > 0 ? t1 : 3) * p[2*i+1];
}
}
ICEs with -O3 -march=armv8.2-a+sve -msve-vector-bits=256 on aarch64. It doesn't
ICE with GCC 9 so marking as regression
ARM64 GCC trunk - cached
Output of ARM64 GCC trunk (Compiler #1)
during GIMPLE pass: vect
<source>: In function 'f':
<source>:1:6: internal compiler error: Segmentation fault
1 | void f (int *restrict p, signed char *restrict b, int *restrict o, int
n)
| ^
