https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126789
--- Comment #6 from Richard Biener <rguenth at gcc dot gnu.org> ---
The following should support the V2SF/V2SI case (I guess just for mask
inter-operability V2SI would be enough, V4HI, V2HI, V8QI, V4QI and V2QI
would be nice as well). Does that look reasonable?
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index f61335af0b9..640b2c0e63f 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -2085,11 +2085,13 @@
(define_mode_attr mmxxmmmode
[(V2HF "V8HF") (V2HI "V8HI") (V2BF "V8BF")
- (V4HF "V8HF") (V4HI "V8HI") (V4BF "V8BF")])
+ (V4HF "V8HF") (V4HI "V8HI") (V4BF "V8BF")
+ (V2SF "V4SF") (V2SI "V4SI")])
(define_mode_attr mmxxmmmodelower
[(V2HF "v8hf") (V2HI "v8hi") (V2BF "v8bf")
- (V4HF "v8hf") (V4HI "v8hi") (V4BF "v8bf")])
+ (V4HF "v8hf") (V4HI "v8hi") (V4BF "v8bf")
+ (V2SF "v4sf") (V2SI "v4si")])
(define_expand "movd_<mode>_to_sse"
[(set (match_operand:<mmxxmmmode> 0 "register_operand")
@@ -2341,6 +2343,24 @@
DONE;
})
+(define_expand "vcond_mask_<mode>qi"
+ [(set (match_operand:V2FI 0 "register_operand")
+ (vec_merge:V2FI
+ (match_operand:V2FI 1 "register_operand")
+ (match_operand:V2FI 2 "register_operand")
+ (match_operand:QI 3 "register_operand")))]
+ "TARGET_MMX_WITH_SSE && TARGET_AVX512VL"
+{
+ rtx op0 = gen_reg_rtx (<mmxxmmmode>mode);
+ operands[1] = lowpart_subreg (<mmxxmmmode>mode, operands[1], <MODE>mode);
+ operands[2] = lowpart_subreg (<mmxxmmmode>mode, operands[2], <MODE>mode);
+ emit_insn (gen_vcond_mask_<mmxxmmmodelower>qi (op0, operands[1],
+ operands[2], operands[3]));
+ emit_move_insn (operands[0],
+ lowpart_subreg (<MODE>mode, op0, <mmxxmmmode>mode));
+ DONE;
+})
+
(define_expand "vec_cmpv2hfqi"
[(set (match_operand:QI 0 "register_operand")
(match_operator:QI 1 ""
