https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127205
Bug ID: 127205
Summary: [17 regression] ivopts changes cause performance
regression on AArch64
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: tree-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: pfustc at gcc dot gnu.org
Target Milestone: ---
The ivopts patch series, including gcc-17-3756-g2c1e9720748,
gcc-17-3757-gabd40f513e0, gcc-17-3758-g0d5fe4ed054 and the follow-up
gcc-17-3764-g0cc9156dbf9 caused performance regressions on AArch64. These can
be seen from multiple benchmarks. The largest performance drop (4% ~ 5%) was
observed in SPEC CPU 2017 549.fotonik3d_r.
Initial analysis:
The goal of the patch series seems to be increasing the possibility of
selecting larger IV sets, mainly by removing additional cost for more
candidates, reducing the penalty of register pressure, etc. However, there're
two problems:
1) The register pressure in the ivopts pass is only an estimate, and it's not
always accurate. Previously, the cost model had an n_cands term, so the cost
gradually increased as more candidates were selected. After removing that,
adding more IVs is free until the estimated register limit is reached. If the
estimation is too optimistic and registers spill in a hot loop, the performance
can drop sharply.
2) Selecting more IV candidates does not necessarily reduce the number of
instructions, especially on AArch64. AArch64 has ldp/stp instructions with
post-index addressing, and the backend can do pair fusion for ldr/str pairs
when they share the same memory base and have adjacent offsets. If ivopts
select more array base IVs, the shared base is no longer exposed to the
backend, so the pair fusion will fail and the post-index addressing will be
lost.
