https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125390
--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Robin Dapp <[email protected]>: https://gcc.gnu.org/g:0b67b93cfe0a67fe431a22b163ac0319fd6ec5da commit r17-3908-g0b67b93cfe0a67fe431a22b163ac0319fd6ec5da Author: Robin Dapp <[email protected]> Date: Mon Aug 31 14:42:10 2026 +0200 RISC-V: Set REGMODE_NATURAL_SIZE for VLS vectors. Following the middle-end changes, this patch makes REGMODE_NATURAL_SIZE return the size of one vector. This implies that subregs of VLS vectors smaller than the vector itself are invalid. Note that this is going to cause a few code-quality regression. Before this change, we could rely on "subregging" our way into vectors but that's not possible anymore. My plan is to fix this by a few adjustments to vec-vec extracts and vec-vec sets during expand, defining a vec-vec vec_init for riscv, as well maybe adding vec_extract and vec_set rtx codes to help with all of that. PR middle-end/125390 gcc/ChangeLog: * config/riscv/riscv-v.cc (shuffle_even_odd_patterns): Adjust check and clarify comment. * config/riscv/riscv.cc (riscv_can_change_mode_class): Allow same-sized vectors. (riscv_regmode_natural_size): Set to "one vector" for VLS modes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/subreg-extract.c: Adjust test expectation. * gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Likewise. * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-evenodd.c: Likewise. * gcc.target/riscv/rvv/autovec/pr125390.c: New test.
