https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127769
Bug ID: 127769
Summary: [X86_64] Missed SLP vectorization for multiply with DI
mode
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: tree-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: vekumar at gcc dot gnu.org
Target Milestone: ---
ref: https://godbolt.org/z/1b5qc85qc
After https://gcc.gnu.org/g:82787e703f9782b113d0ddf6944b50814986205f
typedef unsigned long long u64;
void
mul64_slp2 (u64 *__restrict r, u64 *a, u64 *b)
{
r[0] = a[0] * b[0];
r[1] = a[1] * b[1];
}
I think we are costings the 64 bit muls more now.
--snip ix86_vector_costs::add_stmt_cost --
case MULT_EXPR:
/* For MULT_HIGHPART_EXPR, x86 only supports pmulhw,
take it as MULT_EXPR. */
case MULT_HIGHPART_EXPR:
if (kind == vector_stmt && GET_MODE_INNER (mode) == DImode)
{
/* ix86_expand_umulvndi_highpart, 4 SImode -> DImode
widening multiplies. */
stmt_cost = ix86_multiplication_cost (ix86_cost, SImode) * 4;
/* 5 shifts by 32bit, 1 and, 4 adds. */
stmt_cost += ix86_vec_cost (mode, ix86_cost->sse_op) * 10;
}
--snip--
GCC 16
------
"mul64_slp2":
vmovdqu xmm0, XMMWORD PTR [rdx]
vpmullq xmm0, xmm0, XMMWORD PTR [rsi]
vmovdqu XMMWORD PTR [rdi], xmm0
ret
GCC trunk
---------
mul64_slp2:
movq (%rsi), %rax
imulq (%rdx), %rax
movq %rax, (%rdi)
movq 8(%rsi), %rax
imulq 8(%rdx), %rax
movq %rax, 8(%rdi)
ret
