https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127865
Bug ID: 127865
Summary: RISC-V: redundant sext.w after AOP patches
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: anton at ozlabs dot org
Target Milestone: ---
Target: riscv
While I was looking for something else, claude noticed that the number of
instructions executed in 541.leela_r went up by +0.3% recently, which it
narrowed to the random() call:
unsigned f4(unsigned *p) { unsigned s1 = p[0], s2 = p[1];
unsigned b = ((s1 << 13) ^ s1) >> 19; s1 = ((s1 & 0xFFFFFFFEU) << 12) ^
b;
b = ((s2 << 2) ^ s2) >> 25; s2 = ((s2 & 0xFFFFFFF8U) << 4) ^
b;
p[0] = s1; p[1] = s2; return s1 ^ s2; }
The issue bisects to de2ea1f8b15f "[RISC-V] Fix remaining AOP related
regressions on the RISC-V port". Building with that commit we see the sign
extension:
f4:
lwu a4,0(a0)
lwu a5,4(a0)
mv a1,a0
slliw a2,a4,13
slliw a3,a5,2
xor t0,a2,a4
andi t1,a4,-2
slliw a0,a5,4
xor t2,a3,a5
andi t4,a0,-128
srliw a6,t0,19
slliw a7,t1,12
srliw t3,t2,25
or t5,a7,a6
or t6,t4,t3
xor a4,t5,t6
sw t5,0(a1)
sext.w a0,a4
sw t6,4(a1)
ret
If I build with 83dbe75bb696 there is no sign extension::
f4:
mv a2,a0
lwu a5,4(a2)
lwu a0,0(a0)
slliw a4,a5,2
slliw a3,a0,13
xor t0,a3,a0
andi t1,a0,-2
xor t2,a4,a5
slliw a1,a5,4
srliw a6,t0,19
slliw a7,t1,12
srliw t3,t2,25
andi t4,a1,-128
or t5,a7,a6
or t6,t4,t3
sw t5,0(a2)
xor a0,t5,t6
sw t6,4(a2)
ret
