https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121662
--- Comment #6 from Oleksandr Kulkov <adamant.pwn at gmail dot com> --- Created attachment 65931 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=65931&action=edit AVX-512 guard benchmark: random updates, read-only and copy-on-write inputs Adding measurements for this tradeoff on a Ryzen 9 7945HX (Zen 4), using GCC 16.2.1 20260810 and: gcc -O3 -march=znver4 -mprefer-vector-width=512 masked-store-guard.c -o masked-store-guard The tested loop is: void guarded(int *p, int n) { for (int i = 0; i < n; ++i) if (p[i] < 100) p[i] = 100; } GCC emits kortestw/je before each masked store. With independently distributed 5% updates, about 44% of 16-lane masks are empty. For an 8 MiB array, medians of 31 interleaved runs were: Input GCC guard Branchless masked 5% random updates, writable 542 us 71 us All masks zero, writable 67 us 71 us All masks zero, read-only 65 us 7055 us All masks zero, copy-on-write 62 us 7226 us The branchless version uses _mm512_mask_storeu_epi32 with the same predicate. Input restoration is outside timing; all outputs are checked. GCC 17.0.0 20261022 also retains the guard with these flags (assembly checked). These cases may be useful when evaluating changes to guard placement/profitability: the sparse-update case exposes branch overhead, while the read-only and copy-on-write cases check that fault-suppression costs remain avoided. The attached self-contained Linux benchmark can be saved as masked-store-guard.c.
