https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128164
Bug ID: 128164
Summary: [17 Regression] ICE: insn does not satisfy its
constraints with vwmacc.vx whose source is the lower
half of the accumulator
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: yuki.tanaka at defaultcase dot de
Target Milestone: ---
#include <riscv_vector.h>
void a(int *p)
{
vint32m2_t c = __riscv_vle32_v_i32m2(p, 8);
vint16m1_t lo =
__riscv_vget_v_i16m2_i16m1(__riscv_vreinterpret_v_i32m2_i16m2(c), 0);
c = __riscv_vwmacc_vx_i32m2(c, 3, lo, 8);
__riscv_vse32_v_i32m2(p, c, 8);
}
-O2 -march=rv64gcv
This is valid code, GCC 16.1 compiles it at all optimization levels. GCC 17
compiles it at -O0 but ICEs at -O1, -O2, -O3 and -Os.
Compiler Explorer:
https://godbolt.org/z/vzT5vd8jP
GCC 17:
<source>: In function 'a':
<source>:10:1: error: insn does not satisfy its constraints:
10 | }
| ^
(insn 15 14 28 2 (set (reg/v:RVVM2SI 98 v2 [orig:135 c ] [135])
(if_then_else:RVVM2SI (unspec:RVVMF16BI [
(const_vector:RVVMF16BI repeat [
(const_int 1 [0x1])
])
(const_int 8 [0x8])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(plus:RVVM2SI (mult:RVVM2SI (sign_extend:RVVM2SI
(vec_duplicate:RVVM1HI (reg:HI 15 a5 [139])))
(sign_extend:RVVM2SI (reg:RVVM1HI 98 v2 [orig:135 c ]
[135])))
(reg/v:RVVM2SI 98 v2 [orig:135 c ] [135]))
(reg/v:RVVM2SI 98 v2 [orig:135 c ] [135]))) "<source>":8:7 15728
{pred_widen_mul_plussrvvm2si_scalar}
(expr_list:REG_EQUAL (if_then_else:RVVM2SI (unspec:RVVMF16BI [
(const_vector:RVVMF16BI repeat [
(const_int 1 [0x1])
])
(const_int 8 [0x8])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(plus:RVVM2SI (mult:RVVM2SI (sign_extend:RVVM2SI (subreg:RVVM1HI
(reg/v:RVVM2SI 98 v2 [orig:135 c ] [135]) 0))
(const_vector:RVVM2SI repeat [
(const_int 3 [0x3])
]))
(reg/v:RVVM2SI 98 v2 [orig:135 c ] [135]))
(reg/v:RVVM2SI 98 v2 [orig:135 c ] [135]))
(nil)))
during RTL pass: reload
<source>:10:1: internal compiler error: in extract_constrain_insn, at
recog.cc:2797
0x7abd9b82a28a __libc_start_main
???:0
/cefs/29/2995f6defe8edcbb468b78d3_riscv64_gcc-trunk-20261025/riscv64-unknown-linux-gnu/bin/../libexec/gcc/riscv64-unknown-linux-gnu/17.0.0/cc1
-quiet -imultilib . -iprefix
/cefs/29/2995f6defe8edcbb468b78d3_riscv64_gcc-trunk-20261025/riscv64-unknown-linux-gnu/bin/../lib/gcc/riscv64-unknown-linux-gnu/17.0.0/
-isysroot
/cefs/29/2995f6defe8edcbb468b78d3_riscv64_gcc-trunk-20261025/riscv64-unknown-linux-gnu/bin/../riscv64-unknown-linux-gnu/sysroot
<source> -quiet -dumpdir /app/ -dumpbase output.c -dumpbase-ext .c
-march=rv64gcv -mabi=lp64d -misa-spec=20191213 -mtls-dialect=trad
-march=rv64imafdcv_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b
-g -O2 -fdiagnostics-color=always -fno-verbose-asm -o /app/output.s
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Compiler returned: 1
vwmaccu.vx, vwmaccsu.vx and vwmaccus.vx ICE the same way. See also PR128162,
where the source is the upper half of the accumulator and GCC 17 emits a
reserved vwmacc.vx instead.
Possibly related to r17-3719-gc69c5e7b8e0 ("RISC-V: Allow RVV register overlap
for vwmacc[u].vx").
