https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128319
Bug ID: 128319
Summary: [17 Regression] RISC-V fails to bootstrap after change
to support xxtvarith
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: bootstrap
Assignee: unassigned at gcc dot gnu.org
Reporter: law at gcc dot gnu.org
Target Milestone: ---
The RISC-V port fails to bootstrap after this change:
commit 4de866e5f4c9c626c0d725c3d7bc4c7071565122
Author: Bohan Lei <[email protected]>
Date: Thu Jul 16 10:34:27 2026 +0800
RISC-V: Add support for xxtvarith
This patch adds intrinsic and auto vectorization (vec_perm) support for
xxtvarith, which is one of XuanTie's vendor vector extensions [1]. This
extension include xt.vile (vector interleave even) and xt.vilo (vector
interleave odd) instructions, that can be used for vector permutations
like [0, 8, 2, 10, 4, 12, 6, 14]. They can be useful for transpose
operations in workloads like x264.
[ ... ]
The error:
../../../gcc/gcc/config/riscv/riscv-v.cc: In function 'bool
riscv_vector::shuffle_interleave_even_odd_patterns(expand_vec_perm_d*)':
../../../gcc/gcc/config/riscv/riscv-v.cc:3683:43: error: bitwise operation
between different enumeration types 'riscv_vector::insn_type' and
'riscv_vector::insn_flags' is deprecated
[-Werror=deprecated-enum-enum-conversion]
3683 | emit_vlmax_insn (icode, __NORMAL_OP_TA2 | BINARY_OP_P, ops);
As the error notes, this code performs a logical operation on distinct enum
types and clearly needs to be fixed.
