https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128445
--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Hongyu Wang <[email protected]>: https://gcc.gnu.org/g:5852873096e16f9bacfc8372bec384f826a3a99a commit r17-6045-g5852873096e16f9bacfc8372bec384f826a3a99a Author: Hongyu Wang <[email protected]> Date: Fri Oct 30 11:18:46 2026 +0530 i386: Avoid xchg reg,reg for register swaps on Intel targets [PR128445] Each result of a register swap depends on only one of the inputs, while on Intel cores since Sandy Bridge the xchg reg,reg uops make both results wait for both inputs, so a swap delays the half that was ready. Add a tune for Core and hybrid tunings that swaps with three moves through a scratch register instead. gcc/ChangeLog: PR target/128445 * config/i386/x86-tune.def (X86_TUNE_AVOID_FALSE_DEP_FOR_XCHG): New tune. * config/i386/i386.h (TARGET_AVOID_FALSE_DEP_FOR_XCHG): New macro. * config/i386/i386.md (swap<mode> to three moves peephole2): New peephole2. gcc/testsuite/ChangeLog: PR target/128445 * gcc.target/i386/pr128445-1.c: New test. * gcc.target/i386/pr128445-2.c: Likewise. * gcc.target/i386/xchg-3.c: Add -mtune=generic.
