[Bug target/128601] New: aarch64: Codegen for merging SVE intrinsics with flipped operands is suboptimal

[acoplan at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128601

            Bug ID: 128601
           Summary: aarch64: Codegen for merging SVE intrinsics with
                    flipped operands is suboptimal
           Product: gcc
           Version: 17.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: acoplan at gcc dot gnu.org
  Target Milestone: ---

Consider the following testcase:

#include <arm_sve.h>
svint8_t add_flipped(svbool_t pg, svint8_t z0, svint8_t z1)
{
    return svadd_m (pg, z1, z0);
}

GCC trunk with -O2 -march=armv8-a+sve generates:

add_flipped:
        mov     z31.d, z0.d
        movprfx z0, z1
        add     z0.b, p0/m, z0.b, z31.b
        ret

but LLVM shows it can be done more simply as:

add_flipped:
        add     z1.b, p0/m, z1.b, z0.b
        mov     z0.d, z1.d
        ret

I think we have the same problem with many other binary operations with merging
predication.  E.g. we have the same issue with SVE2 addp, for example:

#include <arm_sve.h>
svint8_t addp_flipped(svbool_t pg, svint8_t z0, svint8_t z1)
{
    return svaddp_m (pg, z1, z0);
}

with -O2 -march=armv8-a+sve2 gives:

addp_flipped:
        mov     z31.d, z0.d
        movprfx z0, z1
        addp    z0.b, p0/m, z0.b, z31.b
        ret

and again LLVM gives the more optimal codegen here:

addp_flipped:
        addp    z1.b, p0/m, z1.b, z0.b
        mov     z0.d, z1.d
        ret