https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90824
--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by jeevitha <[email protected]>: https://gcc.gnu.org/g:7383b183e08c7a94fc51d6db89127f7850ef7bc1 commit r17-6114-g7383b183e08c7a94fc51d6db89127f7850ef7bc1 Author: Jeevitha <[email protected]> Date: Tue Nov 10 02:46:24 2026 -0500 rs6000: Improve SFmode splat code generation on Power7/Power8 [PR90824] Use lfiwzx and xxspltw on Power7, and lxsiwzx and xxspltw on Power8, to improve vector splat code generation for SFmode values loaded from memory. This replaces the previous load, conversion and splat sequence. Allow SFmode splat inputs on all VSX targets and use the vsx_splat_v4sf pattern for vector initialization. For register inputs keep the existing conversion and splat sequence. 2026-11-10 Jeevitha Palanisamy <[email protected]> gcc/ PR target/90824 * config/rs6000/predicates.md (splat_input_operand): Allow SFmode with TARGET_VSX instead of TARGET_P9_VECTOR. * config/rs6000/rs6000.cc (rs6000_expand_vector_init): Use vsx_splat_v4sf for all V4SFmode splats. * config/rs6000/vsx.md (vsx_splat_v4sf): Enable for all VSX targets. Add Power7 and Power8 memory-load alternatives. gcc/testsuite/ PR target/90824 * gcc.target/powerpc/pr90824-1.c: New test. * gcc.target/powerpc/pr90824-2.c: New test.
