andsi3_internal7 and andsi3_internal8 generate invalid LT and GT condition
codes. This is because these bits of the condition register are set from
all 64 bits of the register in 64-bit mode. I don't believe it is possible
to have all of EQ, LT and GT correct using only two rlwinm instructions in
the mask_operand_wrap case.
Causes failure of gcc.c-torture/execute/930718-1.c
--
Summary: invalid rlwinm patterns
Product: gcc
Version: 4.0.0
Status: UNCONFIRMED
Keywords: wrong-code
Severity: critical
Priority: P2
Component: target
AssignedTo: amodra at bigpond dot net dot au
ReportedBy: amodra at bigpond dot net dot au
CC: gcc-bugs at gcc dot gnu dot org
GCC target triplet: powerpc64-*-linux
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19147
