[Bug target/19235] [4.0 regression] GCC generates SSE2 instructions for AthlonXP which doesn't support them.

[cvs-commit at gcc dot gnu dot org]

------- Additional Comments From cvs-commit at gcc dot gnu dot org  2005-01-04 
10:01 -------
Subject: Bug 19235

CVSROOT:        /cvs/gcc
Module name:    gcc
Changes by:     [EMAIL PROTECTED]       2005-01-04 10:00:57

Modified files:
        gcc            : ChangeLog 
        gcc/config/i386: i386.md 

Log message:
        PR target/19235
        * config/i386/i386.md (movdi_2): Separate SSE1 and SSE2 alternatives.
        (mov<MMXMODEI>_internal): Likewise.
        (movdf_nointeger): Prefer Y while not preferring, but allowing, x.
        Add V2SF case; use it for SSE1; don't use TI.
        (movdf_integer): Likewise.
        (mov<SSEMODEI>_internal, movti_internal): Force V4SF for SSE1.

Patches:
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&r1=2.7014&r2=2.7015
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/i386/i386.md.diff?cvsroot=gcc&r1=1.597&r2=1.598



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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19235