https://gcc.gnu.org/g:522bd06b7abf4de674693dc57569547e6de09306
commit 522bd06b7abf4de674693dc57569547e6de09306 Author: Michael Meissner <meiss...@linux.ibm.com> Date: Fri Mar 8 23:14:31 2024 -0500 Add -mcpu=future support. This patch adds the future option to the -mcpu= and -mtune= switches. This patch treats the future like a power11 in terms of costs and reassociation width. This patch issues a ".machine future" to the assembly file if you use -mcpu=power11. This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. 2024-03-08 Michael Meissner <meiss...@linux.ibm.com> gcc/ * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define _ARCH_PWR_FUTURE if -mcpu=future. * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. (POWERPC_MASKS): Add future isa bit. (power11 cpu): Add future definition. * rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future support. (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add future. * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. Diff: --- gcc/config/rs6000/rs6000-c.cc | 2 ++ gcc/config/rs6000/rs6000-cpus.def | 5 +++++ gcc/config/rs6000/rs6000-opts.h | 3 ++- gcc/config/rs6000/rs6000-string.cc | 1 + gcc/config/rs6000/rs6000-tables.opt | 3 +++ gcc/config/rs6000/rs6000.cc | 26 ++++++++++++++++++++------ gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 3 +++ gcc/doc/invoke.texi | 2 +- 9 files changed, 38 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index ebed8b9554a..d15bb85743c 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -449,6 +449,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); if ((flags & OPTION_MASK_POWER11) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11"); + if ((flags & OPTION_MASK_FUTURE) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 3237a5ada30..47365534af8 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -89,6 +89,9 @@ #define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \ | OPTION_MASK_POWER11) +#define ISA_FUTURE_MASKS_SERVER (ISA_POWER11_MASKS_SERVER \ + | OPTION_MASK_FUTURE) + /* Flags that need to be turned off if -mno-vsx. */ #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_KEYWORD \ @@ -127,6 +130,7 @@ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_FLOAT128_KEYWORD \ | OPTION_MASK_FPRND \ + | OPTION_MASK_FUTURE \ | OPTION_MASK_POWER10 \ | OPTION_MASK_POWER11 \ | OPTION_MASK_P10_FUSION \ @@ -262,3 +266,4 @@ RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER) +RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 4f5af57ae1a..d6c766309aa 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -68,7 +68,8 @@ enum processor_type PROCESSOR_CELL, PROCESSOR_PPCA2, PROCESSOR_TITAN, - PROCESSOR_POWER11 + PROCESSOR_POWER11, + PROCESSOR_FUTURE }; diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 9c8a81172e3..e74ccf41937 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -965,6 +965,7 @@ expand_compare_loop (rtx operands[]) case PROCESSOR_POWER9: case PROCESSOR_POWER10: case PROCESSOR_POWER11: + case PROCESSOR_FUTURE: if (bytes_is_const) max_bytes = 191; else diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 7e5bb6e7658..f009c4e5718 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -200,3 +200,6 @@ Enum(rs6000_cpu_opt_value) String(rs64) Value(56) EnumValue Enum(rs6000_cpu_opt_value) String(power11) Value(57) +EnumValue +Enum(rs6000_cpu_opt_value) String(future) Value(58) + diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 71845aa06a4..be30d9e533f 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1067,7 +1067,7 @@ struct processor_costs power9_cost = { COSTS_N_INSNS (3), /* SF->DF convert */ }; -/* Instruction costs on POWER10/POWER11 processors. */ +/* Instruction costs on POWER10/POWER11/FUTURE processors. */ static const struct processor_costs power10_cost = { COSTS_N_INSNS (2), /* mulsi */ @@ -4380,7 +4380,8 @@ rs6000_option_override_internal (bool global_init_p) if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION)) { if (rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE) rs6000_isa_flags |= OPTION_MASK_P10_FUSION; else rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION; @@ -4410,6 +4411,7 @@ rs6000_option_override_internal (bool global_init_p) && rs6000_tune != PROCESSOR_POWER9 && rs6000_tune != PROCESSOR_POWER10 && rs6000_tune != PROCESSOR_POWER11 + && rs6000_tune != PROCESSOR_FUTURE && rs6000_tune != PROCESSOR_PPCA2 && rs6000_tune != PROCESSOR_CELL && rs6000_tune != PROCESSOR_PPC476); @@ -4425,6 +4427,7 @@ rs6000_option_override_internal (bool global_init_p) || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_PPCE500MC || rs6000_tune == PROCESSOR_PPCE500MC64 || rs6000_tune == PROCESSOR_PPCE5500 @@ -4725,6 +4728,7 @@ rs6000_option_override_internal (bool global_init_p) case PROCESSOR_POWER10: case PROCESSOR_POWER11: + case PROCESSOR_FUTURE: rs6000_cost = &power10_cost; break; @@ -5884,6 +5888,8 @@ rs6000_machine_from_flags (void) /* Disable the flags that should never influence the .machine selection. */ flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL); + if ((flags & (ISA_FUTURE_MASKS_SERVER & ~ISA_POWER11_MASKS_SERVER)) != 0) + return "future"; if ((flags & (ISA_POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0) return "power11"; if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) @@ -10133,6 +10139,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, case PROCESSOR_POWER9: case PROCESSOR_POWER10: case PROCESSOR_POWER11: + case PROCESSOR_FUTURE: if (DECIMAL_FLOAT_MODE_P (mode)) return 1; if (VECTOR_MODE_P (mode)) @@ -18215,7 +18222,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, /* Separate a load from a narrower, dependent store. */ if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE) && GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (dep_insn)) == SET && MEM_P (XEXP (PATTERN (insn), 1)) @@ -18255,6 +18263,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) @@ -18830,6 +18839,7 @@ rs6000_issue_rate (void) return 6; case PROCESSOR_POWER10: case PROCESSOR_POWER11: + case PROCESSOR_FUTURE: return 8; default: return 1; @@ -19548,7 +19558,8 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose, /* Do Power10 dependent reordering. */ if (last_scheduled_insn && (rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11)) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE)) power10_sched_reorder (ready, n_ready - 1); return rs6000_issue_rate (); @@ -19574,7 +19585,8 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready, if (last_scheduled_insn && (rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11)) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE)) return power10_sched_reorder (ready, *pn_ready - 1); return cached_can_issue_more; @@ -22792,7 +22804,8 @@ rs6000_register_move_cost (machine_mode mode, out to be a nop. */ if (rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE) ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode); else ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode); @@ -24450,6 +24463,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true }, { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, + { "future", OPTION_MASK_FUTURE, false, true }, { "power10", OPTION_MASK_POWER10, false, true }, { "power11", OPTION_MASK_POWER11, false, true }, { "hard-dfp", OPTION_MASK_DFP, false, true }, diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ea4add5b283..abc809448ad 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -351,7 +351,7 @@ ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, power4,power5,power6,power7,power8,power9,power10, - rs64a,mpccore,cell,ppca2,titan,power11" + rs64a,mpccore,cell,ppca2,titan,power11,future" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index e7a4e4a2ddd..621ebd65a88 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -584,6 +584,9 @@ Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved mpower11 Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>) +mfuture +Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>) + mprefixed Target Mask(PREFIXED) Var(rs6000_isa_flags) Generate (do not generate) prefixed memory instructions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c10e13e3735..ba9518682cc 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -31153,7 +31153,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, -@samp{power9}, @samp{power10}, @samp{power11}, +@samp{power9}, @samp{power10}, @samp{power11}, @samp{future}, @samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le}, @samp{rs64}, and @samp{native}.