https://gcc.gnu.org/g:145bc7b00c10cf6e59897aba7f61c3a24c85ca0b
commit 145bc7b00c10cf6e59897aba7f61c3a24c85ca0b
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Mar 21 23:49:02 2024 -0400
Add support for XVRL instruction.
2024-03-21 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/altivec.md (futue_xvrlw): New insn.
Diff:
---
gcc/config/rs6000/altivec.md | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 4d4c94ff0a0..afe3d72316c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,6 +1883,20 @@
}
[(set_attr "type" "vecperm")])
+;; -mcpu=future adds a vector rotate left word variant. There is no vector
+;; byte/half-word/double-word/quad-word rotate left. This insn occurs before
+;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+(define_insn "*future_xvrlw"
+ [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
+ (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
+ (match_operand:V4SI 2 "register_operand" "v,wa")))]
+ "TARGET_FUTURE"
+ "@
+ vrlw %0,%1,%2
+ xvrlw %x0,%x1,%x2"
+ [(set_attr "type" "vecsimple")])
+
(define_insn "altivec_vrl<VI_char>"
[(set (match_operand:VI2 0 "register_operand" "=v")
(rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
