https://gcc.gnu.org/g:0995cf8ede2865c37becd0e8c76ca78a6f64901d
commit 0995cf8ede2865c37becd0e8c76ca78a6f64901d
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri Mar 22 14:24:37 2024 -0400
Revert all changes
Diff:
---
gcc/config/rs6000/altivec.md | 14 ---
gcc/config/rs6000/constraints.md | 10 --
gcc/config/rs6000/predicates.md | 52 +---------
gcc/config/rs6000/rs6000-builtin.cc | 17 ---
gcc/config/rs6000/rs6000-builtins.def | 10 --
gcc/config/rs6000/rs6000-gen-builtins.cc | 35 +------
gcc/config/rs6000/rs6000-string.cc | 1 -
gcc/config/rs6000/rs6000.cc | 40 -------
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 156 +++-------------------------
gcc/config/rs6000/rs6000.opt | 4 -
gcc/config/rs6000/vsx.md | 122 ++++------------------
gcc/doc/extend.texi | 24 -----
gcc/testsuite/gcc.target/powerpc/lxvrl.c | 32 ------
gcc/testsuite/gcc.target/powerpc/subfus-1.c | 32 ------
gcc/testsuite/gcc.target/powerpc/subfus-2.c | 32 ------
gcc/testsuite/lib/target-supports.exp | 12 ---
17 files changed, 40 insertions(+), 554 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index bf01af15286..4d4c94ff0a0 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,20 +1883,6 @@
}
[(set_attr "type" "vecperm")])
-;; -mcpu=future adds a vector rotate left word variant. There is no vector
-;; byte/half-word/double-word/quad-word rotate left. This insn occurs before
-;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-(define_insn "*xvrlw"
- [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
- (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
- (match_operand:V4SI 2 "register_operand" "v,wa")))]
- "TARGET_FUTURE"
- "@
- vrlw %0,%1,%2
- xvrlw %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")])
-
(define_insn "altivec_vrl<VI_char>"
[(set (match_operand:VI2 0 "register_operand" "=v")
(rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 4d8d21fd6bb..277a30a8245 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,16 +222,6 @@
"An IEEE 128-bit constant that can be loaded into VSX registers."
(match_operand 0 "easy_vector_constant_ieee128"))
-(define_constraint "eU"
- "@internal integer constant that can be loaded with paddis"
- (and (match_code "const_int")
- (match_operand 0 "paddis_operand")))
-
-(define_constraint "eV"
- "@internal integer constant that can be loaded with paddis + paddi"
- (and (match_code "const_int")
- (match_operand 0 "paddis_paddi_operand")))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 0b7c0bf4b0f..b325000690b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,53 +369,6 @@
return SIGNED_INTEGER_34BIT_P (INTVAL (op));
})
-;; Return 1 if op is a 64-bit constant that uses the paddis instruction
-(define_predicate "paddis_operand"
- (match_code "const_int")
-{
- if (!TARGET_PADDIS && TARGET_POWERPC64)
- return 0;
-
- /* If addi, addis, or paddi can handle the number, don't return true. */
- HOST_WIDE_INT value = INTVAL (op);
- if (SIGNED_INTEGER_34BIT_P (value))
- return false;
-
- /* If the number is too large for padds, return false. */
- if (!SIGNED_INTEGER_32BIT_P (value >> 32))
- return false;
-
- /* If the bottom 32-bits are non-zero, paddis can't handle it. */
- if ((value & HOST_WIDE_INT_C(0xffffffff)) != 0)
- return false;
-
- return true;
-})
-
-;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
-;; addi/addis/paddi instruction combination.
-(define_predicate "paddis_paddi_operand"
- (match_code "const_int")
-{
- if (!TARGET_PADDIS && TARGET_POWERPC64)
- return 0;
-
- /* If addi, addis, or paddi can handle the number, don't return true. */
- HOST_WIDE_INT value = INTVAL (op);
- if (SIGNED_INTEGER_34BIT_P (value))
- return false;
-
- /* If the number is too large for padds, return false. */
- if (!SIGNED_INTEGER_32BIT_P (value >> 32))
- return false;
-
- /* If the bottom 32-bits are zero, we can use paddis alone to handle it. */
- if ((value & HOST_WIDE_INT_C(0xffffffff)) == 0)
- return false;
-
- return true;
-})
-
;; Return 1 if op is a register that is not special.
;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1097,10 +1050,7 @@
(if_then_else (match_code "const_int")
(match_test "satisfies_constraint_I (op)
|| satisfies_constraint_L (op)
- || satisfies_constraint_eI (op)
- || satisfies_constraint_eU (op)
- || satisfies_constraint_eV (op)")
-
+ || satisfies_constraint_eI (op)")
(match_operand 0 "gpc_reg_operand")))
;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 1af38698bf3..976a42a74cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -139,17 +139,6 @@ rs6000_invalid_builtin (enum rs6000_gen_builtins fncode)
case ENB_MMA:
error ("%qs requires the %qs option", name, "-mmma");
break;
- case ENB_FUTURE:
- error ("%qs requires the %qs option", name, "-mcpu=future");
- break;
- case ENB_FUTURE_64:
- error ("%qs requires the %qs option and either the %qs or %qs option",
- name, "-mcpu=future", "-m64", "-mpowerpc64");
- break;
- case ENB_DM:
- error ("%qs requires the %qs or %qs options", name, "-mcpu=future",
- "-mdense-math");
- break;
default:
case ENB_ALWAYS:
gcc_unreachable ();
@@ -205,12 +194,6 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
return TARGET_HTM;
case ENB_MMA:
return TARGET_MMA;
- case ENB_FUTURE:
- return TARGET_FUTURE;
- case ENB_FUTURE_64:
- return TARGET_FUTURE && TARGET_POWERPC64;
- case ENB_DM:
- return TARGET_DENSE_MATH;
default:
gcc_unreachable ();
}
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 437ab0e09e9..3bc7fed6956 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -139,8 +139,6 @@
; endian Needs special handling for endianness
; ibmld Restrict usage to the case when TFmode is IBM-128
; ibm128 Restrict usage to the case where __ibm128 is supported or if ibmld
-; future Restrict usage to future instructions
-; dm Restrict usage to dense math
;
; Each attribute corresponds to extra processing required when
; the built-in is expanded. All such special processing should
@@ -4133,11 +4131,3 @@
void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
STXVP nothing {mma,pair}
-
-[future]
- const signed int __builtin_saturate_subtract32 (signed int, signed int);
- SAT_SUBSI sat_subsi3 {}
-
-[future-64]
- const signed long __builtin_saturate_subtract64 (signed long, signed long);
- SAT_SUBDI sat_subdi3 {}
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc
b/gcc/config/rs6000/rs6000-gen-builtins.cc
index acd65d4bd0a..e32d1e2d134 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.cc
+++ b/gcc/config/rs6000/rs6000-gen-builtins.cc
@@ -233,9 +233,6 @@ enum bif_stanza
BSTZ_P10,
BSTZ_P10_64,
BSTZ_MMA,
- BSTZ_FUTURE,
- BSTZ_FUTURE_64,
- BSTZ_DM,
NUMBIFSTANZAS
};
@@ -269,10 +266,7 @@ static stanza_entry stanza_map[NUMBIFSTANZAS] =
{ "htm", BSTZ_HTM },
{ "power10", BSTZ_P10 },
{ "power10-64", BSTZ_P10_64 },
- { "mma", BSTZ_MMA },
- { "future", BSTZ_FUTURE },
- { "future-64", BSTZ_FUTURE_64 },
- { "dm", BSTZ_DM },
+ { "mma", BSTZ_MMA }
};
static const char *enable_string[NUMBIFSTANZAS] =
@@ -297,10 +291,7 @@ static const char *enable_string[NUMBIFSTANZAS] =
"ENB_HTM",
"ENB_P10",
"ENB_P10_64",
- "ENB_MMA",
- "ENB_FUTURE",
- "ENB_FUTURE_64",
- "ENB_DM",
+ "ENB_MMA"
};
/* Function modifiers provide special handling for const, pure, and fpmath
@@ -404,8 +395,6 @@ struct attrinfo
bool isendian;
bool isibmld;
bool isibm128;
- bool isfuture;
- bool isdm;
};
/* Fields associated with a function prototype (bif or overload). */
@@ -1488,8 +1477,7 @@ parse_bif_attrs (attrinfo *attrptr)
"ldvec = %d, stvec = %d, reve = %d, pred = %d, htm = %d, "
"htmspr = %d, htmcr = %d, mma = %d, quad = %d, pair = %d, "
"mmaint = %d, no32bit = %d, 32bit = %d, cpu = %d, ldstmask = %d, "
- "lxvrse = %d, lxvrze = %d, endian = %d, ibmdld = %d, ibm128 = %d,",
- "future = %d, dm = %d.\n",
+ "lxvrse = %d, lxvrze = %d, endian = %d, ibmdld = %d, ibm128 = %d.\n",
attrptr->isinit, attrptr->isset, attrptr->isextract,
attrptr->isnosoft, attrptr->isldvec, attrptr->isstvec,
attrptr->isreve, attrptr->ispred, attrptr->ishtm, attrptr->ishtmspr,
@@ -1497,7 +1485,7 @@ parse_bif_attrs (attrinfo *attrptr)
attrptr->ismmaint, attrptr->isno32bit, attrptr->is32bit,
attrptr->iscpu, attrptr->isldstmask, attrptr->islxvrse,
attrptr->islxvrze, attrptr->isendian, attrptr->isibmld,
- attrptr->isibm128, attrptr->isfuture, attrptr->isdm);
+ attrptr->isibm128);
#endif
return PC_OK;
@@ -2269,10 +2257,7 @@ write_decls (void)
fprintf (header_file, " ENB_HTM,\n");
fprintf (header_file, " ENB_P10,\n");
fprintf (header_file, " ENB_P10_64,\n");
- fprintf (header_file, " ENB_MMA,\n");
- fprintf (header_file, " ENB_FUTURE,\n");
- fprintf (header_file, " ENB_FUTURE_64,\n");
- fprintf (header_file, " ENB_DM\n");
+ fprintf (header_file, " ENB_MMA\n");
fprintf (header_file, "};\n\n");
fprintf (header_file, "#define PPC_MAXRESTROPNDS 3\n");
@@ -2316,8 +2301,6 @@ write_decls (void)
fprintf (header_file, "#define bif_endian_bit\t\t(0x00200000)\n");
fprintf (header_file, "#define bif_ibmld_bit\t\t(0x00400000)\n");
fprintf (header_file, "#define bif_ibm128_bit\t\t(0x00800000)\n");
- fprintf (header_file, "#define bif_future_bit\t\t(0x01000000)\n");
- fprintf (header_file, "#define bif_dm_bit\t\t(0x02000000)\n");
fprintf (header_file, "\n");
fprintf (header_file,
"#define bif_is_init(x)\t\t((x).bifattrs & bif_init_bit)\n");
@@ -2367,10 +2350,6 @@ write_decls (void)
"#define bif_is_ibmld(x)\t((x).bifattrs & bif_ibmld_bit)\n");
fprintf (header_file,
"#define bif_is_ibm128(x)\t((x).bifattrs & bif_ibm128_bit)\n");
- fprintf (header_file,
- "#define bif_is_future(x)\t((x).bifattrs & bif_future_bit)\n");
- fprintf (header_file,
- "#define bif_is_dm(x)\t((x).bifattrs & bif_dm_bit)\n");
fprintf (header_file, "\n");
fprintf (header_file,
@@ -2569,10 +2548,6 @@ write_bif_static_init (void)
fprintf (init_file, " | bif_ibmld_bit");
if (bifp->attrs.isibm128)
fprintf (init_file, " | bif_ibm128_bit");
- if (bifp->attrs.isfuture)
- fprintf (init_file, " | bif_future_bit");
- if (bifp->attrs.isdm)
- fprintf (init_file, " | bif_dm_bit");
fprintf (init_file, ",\n");
fprintf (init_file, " /* restr_opnd */\t{%d, %d, %d},\n",
bifp->proto.restr_opnd[0], bifp->proto.restr_opnd[1],
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index c6737e66cbe..e74ccf41937 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -2787,7 +2787,6 @@ expand_block_move (rtx operands[], bool might_overlap)
if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX
&& TARGET_BLOCK_OPS_VECTOR_PAIR
- && TARGET_POWERPC64
&& bytes >= 32
&& (align >= 256 || !STRICT_ALIGNMENT))
{
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index b34bd0f0899..573602d0c11 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4307,16 +4307,6 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_PCREL;
}
-
- /* -mpaddis requires -mcpu=future. */
- if (TARGET_PADDIS && !TARGET_FUTURE)
- {
- if (OPTION_SET_P (TARGET_PADDIS))
- error ("%qs requires %qs", "-mpaddis", "-mcpu=future");
-
- TARGET_PADDIS = 0;
- }
-
/* Print the options after updating the defaults. */
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
@@ -6127,17 +6117,6 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))
return 1;
- /* PADDIS support. */
- else if (TARGET_PADDIS && TARGET_POWERPC64
- && !IN_RANGE (value >> 32, -1, 0)
- && (SIGNED_INTEGER_32BIT_P (value >> 32)))
- {
- fprintf (stderr, "=== 0x%lx ===\n", (long)value);
- return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0
- ? 1
- : 2);
- }
-
else if (TARGET_POWERPC64)
{
int num_insns = 0;
@@ -6158,14 +6137,6 @@ num_insns_constant_multi (HOST_WIDE_INT value,
machine_mode mode)
{
int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
int total = 0;
- if (nregs == 1
- && TARGET_PADDIS && TARGET_POWERPC64
- && !IN_RANGE (value >> 32, -1, 0)
- && SIGNED_INTEGER_32BIT_P (value >> 32))
- return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0
- ? 1
- : 2);
-
while (nregs-- > 0)
{
HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD);
@@ -14240,14 +14211,6 @@ print_operand (FILE *file, rtx x, int code)
fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4);
return;
- case 'B':
- /* Upper 32-bits of a constant. */
- if (!CONST_INT_P (x))
- output_operand_lossage ("Not a constant.");
-
- fprintf (file, "%" HOST_LONG_FORMAT "d", INTVAL (x) >> 32);
- return;
-
case 'D':
/* Like 'J' but get to the GT bit only. */
if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
@@ -24782,9 +24745,6 @@ static struct rs6000_opt_var const rs6000_opt_vars[] =
{ "speculate-indirect-jumps",
offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
- { "paddis",
- offsetof (struct gcc_options, x_TARGET_PADDIS),
- offsetof (struct cl_target_option, x_TARGET_PADDIS), },
};
/* Inner function to handle attribute((target("..."))) and #pragma GCC target
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 693de2ba72c..67ef3d3a7d0 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2495,7 +2495,6 @@ typedef struct GTY(()) machine_function
(HOST_WIDE_INT_1 << ((N)-1)) - 1)
#define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16)
-#define SIGNED_INTEGER_32BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 32)
#define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34)
/* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f96a228d1ba..2ccd83c9092 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -357,7 +357,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,paddis"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -405,11 +405,6 @@
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
-
- (and (eq_attr "isa" "paddis")
- (match_test "TARGET_PADDIS"))
- (const_int 1)
-
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
@@ -1815,42 +1810,17 @@
})
(define_insn "*add<mode>3"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r,r,b")
- (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b,b,b")
- (match_operand:GPR 2 "add_operand" "r,I,L,eI,eU,eV")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
+ (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b")
+ (match_operand:GPR 2 "add_operand" "r,I,L,eI")))]
""
"@
add %0,%1,%2
addi %0,%1,%2
addis %0,%1,%v2
- addi %0,%1,%2
- paddis %0,%1,%B2
- #"
+ addi %0,%1,%2"
[(set_attr "type" "add")
- (set_attr "isa" "*,*,*,p10,paddis,paddis")
- (set_attr "length" "*,*,*,*,12,24")
- (set_attr "prefixed" "*,*,*,*,yes,yes")
- (set_attr "maybe_prefixed" "*,*,*,*,no,no")])
-
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand")
- (plus:DI (match_operand:DI 1 "gpc_reg_operand")
- (match_operand:DI 2 "paddis_paddi_operand")))]
- "TARGET_PADDIS && TARGET_POWERPC64"
- [(set (match_dup 3)
- (plus:DI (match_dup 1)
- (match_dup 4)))
- (set (match_dup 0)
- (plus:DI (match_dup 3)
- (match_dup 5)))]
-{
- HOST_WIDE_INT value = INTVAL (operands[2]);
- operands[3] = (can_create_pseudo_p ()
- ? gen_reg_rtx (DImode)
- : operands[0]);
- operands[4] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));
- operands[5] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));
-})
+ (set_attr "isa" "*,*,*,p10")])
(define_insn "*addsi3_high"
[(set (match_operand:SI 0 "gpc_reg_operand" "=b")
@@ -9865,7 +9835,7 @@
DONE;
})
-;; GPR store GPR load GPR move GPR paddis GPR paddis+paddi
+;; GPR store GPR load GPR move
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9875,7 +9845,7 @@
;; VSX->GPR GPR->VSX
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=YZ, r, r, r, b,
+ "=YZ, r, r,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9884,7 +9854,7 @@
r, *h, *h,
?r, ?wa")
(match_operand:DI 1 "input_operand"
- "r, YZ, r, eU, eV,
+ "r, YZ, r,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9899,8 +9869,6 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
- paddis %0,0,%B1
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9926,7 +9894,7 @@
mfvsrd %0,%x1
mtvsrd %x0,%1"
[(set_attr "type"
- "store, load, *, *, *,
+ "store, load, *,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9936,7 +9904,7 @@
mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "length"
- "*, *, *, 12, 24,
+ "*, *, *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9945,32 +9913,14 @@
*, *, *,
*, *")
(set_attr "isa"
- "*, *, *, paddis, paddis,
+ "*, *, *,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *,
p7v, p7v,
*, *, *,
- p8v, p8v")
- (set_attr "prefixed"
- "*, *, *, yes, yes,
- *, *, *, *,
- *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *,
- *, *, *,
- *, *")
- (set_attr "maybe_prefixed"
- "*, *, *, no, no,
- *, *, *, *,
- *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *,
- *, *, *,
- *, *")])
+ p8v, p8v")])
; Some DImode loads are best done as a load of -1 followed by a mask
; instruction.
@@ -9988,26 +9938,6 @@
(match_dup 1)))]
"")
-;; Split a constant that can be generated by a paddis and paddi into 2
-;; instructions.
-(define_split
- [(set (match_operand:DI 0 "int_reg_operand")
- (match_operand:DI 1 "paddis_paddi_operand"))]
- "TARGET_PADDIS && TARGET_POWERPC64"
- [(set (match_dup 2)
- (match_dup 3))
- (set (match_dup 0)
- (plus:DI (match_dup 2)
- (match_dup 4)))]
-{
- HOST_WIDE_INT value = INTVAL (operands[1]);
- operands[2] = (can_create_pseudo_p ()
- ? gen_reg_rtx (DImode)
- : operands[0]);
- operands[3] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));
- operands[4] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));
-})
-
;; Split a load of a large constant into the appropriate five-instruction
;; sequence. Handle anything in a constant number of insns.
;; When non-easy constants can go in the TOC, this should use
@@ -15892,66 +15822,6 @@
}
[(set_attr "type" "load")])
-;; Signed saturation.
-
-;; The subfus instruction is defined as: SUBFUS RT,L,RA,RB. The extended
-;; mnemonic that we use (subdus and subwus) has the arguments RA and RB
-;; reversed (so it becomes a subtract instead of subtract from).
-
-(define_insn "sat_sub<mode>3"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
- (match_operand:GPR 2 "gpc_reg_operand" "r")))]
- "TARGET_FUTURE"
- "sub<wd>us %0,%1,%2"
- [(set_attr "type" "add")])
-
-(define_insn_and_split "*sat_sub<mode>3_dot"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
- (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (clobber (match_scratch:GPR 0 "=r,r"))]
- "TARGET_FUTURE"
- "@
- sub<wd>us. %0,%1,%2
- #"
- "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
- [(set (match_dup 0)
- (ss_minus:GPR (match_dup 1)
- (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- ""
- [(set_attr "type" "add")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn_and_split "*sat_sub<mode>3_dot2"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
- (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
- (const_int 0)))
- (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
- (ss_minus:GPR (match_dup 1)
- (match_dup 2)))]
- "TARGET_FUTURE"
- "@
- sub<wd>us. %0,%1,%2
- #"
- "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
- [(set (match_dup 0)
- (ss_minus:GPR (match_dup 1)
- (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- ""
- [(set_attr "type" "add")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
(include "sync.md")
(include "vector.md")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index cfefe65afbe..621ebd65a88 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -603,10 +603,6 @@ mmma
Target Mask(MMA) Var(rs6000_isa_flags)
Generate (do not generate) MMA instructions.
-mpaddis
-Target Undocumented Var(TARGET_PADDIS) Save
-Generate (do not generate) the paddis instruction.
-
mrelative-jumptables
Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9520191e613..f135fa079bd 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5629,32 +5629,20 @@
DONE;
})
-;; Load VSX Vector with Length. If we have lxvrl, we don't have to do an
-;; explicit shift left into a pseudo.
+;; Load VSX Vector with Length
(define_expand "lxvl"
- [(use (match_operand:V16QI 0 "vsx_register_operand"))
- (use (match_operand:DI 1 "gpc_reg_operand"))
- (use (match_operand:DI 2 "gpc_reg_operand"))]
+ [(set (match_dup 3)
+ (ashift:DI (match_operand:DI 2 "register_operand")
+ (const_int 56)))
+ (set (match_operand:V16QI 0 "vsx_register_operand")
+ (unspec:V16QI
+ [(match_operand:DI 1 "gpc_reg_operand")
+ (mem:V16QI (match_dup 1))
+ (match_dup 3)]
+ UNSPEC_LXVL))]
"TARGET_P9_VECTOR && TARGET_64BIT"
{
- rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
- rtx len;
-
- if (TARGET_FUTURE)
- len = shift_len;
- else
- {
- len = gen_reg_rtx (DImode);
- emit_insn (gen_rtx_SET (len, shift_len));
- }
-
- rtx dest = operands[0];
- rtx addr = operands[1];
- rtx mem = gen_rtx_MEM (V16QImode, addr);
- rtvec rv = gen_rtvec (3, addr, mem, len);
- rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);
- emit_insn (gen_rtx_SET (dest, lxvl));
- DONE;
+ operands[3] = gen_reg_rtx (DImode);
})
(define_insn "*lxvl"
@@ -5678,34 +5666,6 @@
"lxvll %x0,%1,%2"
[(set_attr "type" "vecload")])
-;; For lxvrl and lxvrll, use the combiner to eliminate the shift. The
-;; define_expand for lxvl will already incorporate the shift in generating the
-;; insn. The lxvll buitl-in function required the user to have already done
-;; the shift. Defining lxvrll this way, will optimize cases where the user has
-;; done the shift immediately before the built-in.
-(define_insn "*lxvrl"
- [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
- (unspec:V16QI
- [(match_operand:DI 1 "gpc_reg_operand" "b")
- (mem:V16QI (match_dup 1))
- (ashift:DI (match_operand:DI 2 "register_operand" "r")
- (const_int 56))]
- UNSPEC_LXVL))]
- "TARGET_FUTURE && TARGET_64BIT"
- "lxvrl %x0,%1,%2"
- [(set_attr "type" "vecload")])
-
-(define_insn "*lxvrll"
- [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
- (unspec:V16QI [(match_operand:DI 1 "gpc_reg_operand" "b")
- (mem:V16QI (match_dup 1))
- (ashift:DI (match_operand:DI 2 "register_operand" "r")
- (const_int 56))]
- UNSPEC_LXVLL))]
- "TARGET_FUTURE"
- "lxvrll %x0,%1,%2"
- [(set_attr "type" "vecload")])
-
;; Expand for builtin xl_len_r
(define_expand "xl_len_r"
[(match_operand:V16QI 0 "vsx_register_operand")
@@ -5737,29 +5697,18 @@
;; Store VSX Vector with Length
(define_expand "stxvl"
- [(use (match_operand:V16QI 0 "vsx_register_operand"))
- (use (match_operand:DI 1 "gpc_reg_operand"))
- (use (match_operand:DI 2 "gpc_reg_operand"))]
+ [(set (match_dup 3)
+ (ashift:DI (match_operand:DI 2 "register_operand")
+ (const_int 56)))
+ (set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand"))
+ (unspec:V16QI
+ [(match_operand:V16QI 0 "vsx_register_operand")
+ (mem:V16QI (match_dup 1))
+ (match_dup 3)]
+ UNSPEC_STXVL))]
"TARGET_P9_VECTOR && TARGET_64BIT"
{
- rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
- rtx len;
-
- if (TARGET_FUTURE)
- len = shift_len;
- else
- {
- len = gen_reg_rtx (DImode);
- emit_insn (gen_rtx_SET (len, shift_len));
- }
-
- rtx src = operands[0];
- rtx addr = operands[1];
- rtx mem = gen_rtx_MEM (V16QImode, addr);
- rtvec rv = gen_rtvec (3, src, mem, len);
- rtx stxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_STXVL);
- emit_insn (gen_rtx_SET (mem, stxvl));
- DONE;
+ operands[3] = gen_reg_rtx (DImode);
})
;; Define optab for vector access with length vectorization exploitation.
@@ -5803,35 +5752,6 @@
"stxvl %x0,%1,%2"
[(set_attr "type" "vecstore")])
-;; For stxvrl and stxvrll, use the combiner to eliminate the shift. The
-;; define_expand for stxvl will already incorporate the shift in generating the
-;; insn. The stxvll buitl-in function required the user to have already done
-;; the shift. Defining stxvrll this way, will optimize cases where the user
-;; has done the shift immediately before the built-in.
-
-(define_insn "*stxvrl"
- [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
- (unspec:V16QI
- [(match_operand:V16QI 0 "vsx_register_operand" "wa")
- (mem:V16QI (match_dup 1))
- (ashift:DI (match_operand:DI 2 "register_operand" "r")
- (const_int 56))]
- UNSPEC_STXVL))]
- "TARGET_FUTURE && TARGET_64BIT"
- "stxvrl %x0,%1,%2"
- [(set_attr "type" "vecstore")])
-
-(define_insn "*stxvrll"
- [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
- (unspec:V16QI [(match_operand:V16QI 0 "vsx_register_operand" "wa")
- (mem:V16QI (match_dup 1))
- (ashift:DI (match_operand:DI 2 "register_operand" "r")
- (const_int 56))]
- UNSPEC_STXVLL))]
- "TARGET_FUTURE"
- "stxvrll %x0,%1,%2"
- [(set_attr "type" "vecstore")])
-
;; Expand for builtin xst_len_r
(define_expand "xst_len_r"
[(match_operand:V16QI 0 "vsx_register_operand" "=wa")
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 713e7ee96c0..7b54a241a7b 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -20963,7 +20963,6 @@ Reverse the bit order of a 64-bit unsigned integer.
* Basic PowerPC Built-in Functions Available on ISA 2.07::
* Basic PowerPC Built-in Functions Available on ISA 3.0::
* Basic PowerPC Built-in Functions Available on ISA 3.1::
-* Basic Built-in Functions that may be available on future PowerPCs::
@end menu
This section describes PowerPC built-in functions that do not require
@@ -21615,29 +21614,6 @@ ISA 3.1 @code{stxvrbx}, @code{stxvrhx},
@code{stxvrwx}, and @code{stxvrdx}
instructions.
@enddefbuiltin
-@node Basic Built-in Functions that may be available on future PowerPCs
-@subsubsection Potential future PowerPC Built-in Functions
-
-The built-in functions described in this section may be available on
-future PowerPC processors. At present, these built-ins exist to
-allowing testing of new instructions. There is no guarantee that
-these instructions will actually be implemented.
-
-The following built-in functions are available on Linux 64-bit systems
-that use a potential future instruction set (@option{-mcpu=future}):
-
-@table @code
-@item int __builtin_saturate_subtract32 (int, int)
-Subtract the second operand from the first operand. If the value
-would be less than 0, then the result is 0 instead of the negative
-value of the subtraction.
-
-@item long __builtin_saturate_subtract64 (long, long)
-Subtract the second operand from the first operand. If the value
-would be less than 0, then the result is 0 instead of the negative
-value of the subtraction.
-@end table
-
@node PowerPC AltiVec/VSX Built-in Functions
@subsection PowerPC AltiVec/VSX Built-in Functions
diff --git a/gcc/testsuite/gcc.target/powerpc/lxvrl.c
b/gcc/testsuite/gcc.target/powerpc/lxvrl.c
deleted file mode 100644
index 71854c50c91..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/lxvrl.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the lxvrl and stxvrl instructions are generated for
- -mcpu=future on memory copy operations. */
-
-#ifndef VSIZE
-#define VSIZE 2
-#endif
-
-#ifndef LSIZE
-#define LSIZE 5
-#endif
-
-struct foo {
- vector unsigned char vc[VSIZE];
- unsigned char leftover[LSIZE];
-};
-
-void memcpy_ptr (struct foo *p, struct foo *q)
-{
- __builtin_memcpy ((void *) p, /* lxvrl and stxvrl. */
- (void *) q,
- (sizeof (vector unsigned char) * VSIZE) + LSIZE);
-}
-
-/* { dg-final { scan-assembler {\mlxvrl\M} } } */
-/* { dg-final { scan-assembler {\mstxvrl\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvl\M} } } */
-/* { dg-final { scan-assembler-not {\mstxvl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/subfus-1.c
b/gcc/testsuite/gcc.target/powerpc/subfus-1.c
deleted file mode 100644
index 535e7f8483d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/subfus-1.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the saturating subtract built-in generates subwus for 32-bit
- subtracts. */
-
-int do_sat_int (int a, int b)
-{
- return __builtin_saturate_subtract32 (a, b); /* subwus */
-}
-
-int do_sat_int_dot (int a, int b, int *p)
-{
- int r = __builtin_saturate_subtract32 (a, b); /* subwus. */
- if (r == 0)
- *p = 0;
-
- return r;
-}
-
-void do_sat_int_dot2 (int a, int b, int *p, int *q)
-{
- if (__builtin_saturate_subtract32 (a, b)) /* subwus. */
- *p = 0;
-
- *q = a + b;
- return;
-}
-
-/* { dg-final { scan-assembler {\msubwus\M} } } */
-/* { dg-final { scan-assembler-not {\msubf\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/subfus-2.c
b/gcc/testsuite/gcc.target/powerpc/subfus-2.c
deleted file mode 100644
index b68e66dd2b0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/subfus-2.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the saturating subtract built-in generates subwus for 64-bit
- subtracts. */
-
-long do_sat_long (long a, long b)
-{
- return __builtin_saturate_subtract64 (a, b); /* subwus */
-}
-
-long do_sat_long_dot (long a, long b, long *p)
-{
- long r = __builtin_saturate_subtract64 (a, b); /* subwus. */
- if (r == 0)
- *p = 0;
-
- return r;
-}
-
-void do_sat_long_dot2 (long a, long b, long *p, long *q)
-{
- if (__builtin_saturate_subtract64 (a, b)) /* subwus. */
- *p = 0;
-
- *q = a + b;
- return;
-}
-
-/* { dg-final { scan-assembler {\msubdus\M} } } */
-/* { dg-final { scan-assembler-not {\msubf\M} } } */
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 6b87d88aa75..14b3737eecf 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7121,18 +7121,6 @@ proc check_effective_target_power11_ok { } {
}
}
-# Return 1 if this is a PowerPC target supporting -mcpu=future which enables
-# the saturating subtract instruction.
-proc check_effective_target_powerpc_future_ok { } {
- return [check_no_compiler_messages powerpc_future_ok object {
- #ifndef _ARCH_PWR_FUTURE
- #error "-mcpu=future is not supported"
- #else
- int dummy;
- #endif
- } "-mcpu=future"]
-}
-
# Return 1 if this is a PowerPC target supporting -mcpu=future which enables
# the dense math operations.
proc check_effective_target_powerpc_dense_math_ok { } {
