https://gcc.gnu.org/g:ec78916bb37bec0cd3ede5c6263387345ce16f94
commit r14-10062-gec78916bb37bec0cd3ede5c6263387345ce16f94
Author: Pan Li <pan2...@intel.com>
Date: Mon Apr 22 09:26:04 2024 +0800
Revert "RISC-V: Support widening register overlap for vf4/vf8"
This reverts commit 303195e2a6b6f0e8f42e0578b61f9f37c6250beb.
Diff:
---
gcc/config/riscv/vector.md | 38 ++++++------
.../gcc.target/riscv/rvv/base/pr112431-16.c | 68 ----------------------
.../gcc.target/riscv/rvv/base/pr112431-17.c | 51 ----------------
.../gcc.target/riscv/rvv/base/pr112431-18.c | 51 ----------------
4 files changed, 18 insertions(+), 190 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f620f13682c..140b4638346 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3754,45 +3754,43 @@
;; Vector Quad-Widening Sign-extend and Zero-extend.
(define_insn "@pred_<optab><mode>_vf4"
- [(set (match_operand:VQEXTI 0 "register_operand" "=vr, vr,
vr, vr, ?&vr, ?&vr")
+ [(set (match_operand:VQEXTI 0 "register_operand" "=&vr,&vr")
(if_then_else:VQEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i,
i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i,
i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i,
i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_extend:VQEXTI
- (match_operand:<V_QUAD_TRUNC> 3 "register_operand" " W43, W43,
W86, W86, vr, vr"))
- (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0,
vu, 0, vu, 0")))]
+ (match_operand:<V_QUAD_TRUNC> 3 "register_operand" " vr, vr"))
+ (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"v<sz>ext.vf4\t%0,%3%p1"
[(set_attr "type" "vext")
- (set_attr "mode" "<MODE>")
- (set_attr "group_overlap" "W43,W43,W86,W86,none,none")])
+ (set_attr "mode" "<MODE>")])
;; Vector Oct-Widening Sign-extend and Zero-extend.
(define_insn "@pred_<optab><mode>_vf8"
- [(set (match_operand:VOEXTI 0 "register_operand" "=vr, vr,
?&vr, ?&vr")
+ [(set (match_operand:VOEXTI 0 "register_operand" "=&vr,&vr")
(if_then_else:VOEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK")
- (match_operand 5 "const_int_operand" " i, i,
i, i")
- (match_operand 6 "const_int_operand" " i, i,
i, i")
- (match_operand 7 "const_int_operand" " i, i,
i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 5 "const_int_operand" " i, i")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_extend:VOEXTI
- (match_operand:<V_OCT_TRUNC> 3 "register_operand" " W87, W87,
vr, vr"))
- (match_operand:VOEXTI 2 "vector_merge_operand" " vu, 0,
vu, 0")))]
+ (match_operand:<V_OCT_TRUNC> 3 "register_operand" " vr, vr"))
+ (match_operand:VOEXTI 2 "vector_merge_operand" " vu, 0")))]
"TARGET_VECTOR"
"v<sz>ext.vf8\t%0,%3%p1"
[(set_attr "type" "vext")
- (set_attr "mode" "<MODE>")
- (set_attr "group_overlap" "W87,W87,none,none")])
+ (set_attr "mode" "<MODE>")])
;; Vector Widening Add/Subtract/Multiply.
(define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
deleted file mode 100644
index 98f42458883..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
-
-#include "riscv_vector.h"
-
-size_t __attribute__ ((noinline))
-sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
- size_t sum5, size_t sum6, size_t sum7)
-{
- return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7;
-}
-
-size_t
-foo (char const *buf, size_t len)
-{
- size_t sum = 0;
- size_t vl = __riscv_vsetvlmax_e8m8 ();
- size_t step = vl * 4;
- const char *it = buf, *end = buf + len;
- for (; it + step <= end;)
- {
- vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
- vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
- vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
- vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
- vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
- vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
- vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
- vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
-
- asm volatile("nop" ::: "memory");
- vint32m4_t vw0 = __riscv_vsext_vf4_i32m4 (v0, vl);
- vint32m4_t vw1 = __riscv_vsext_vf4_i32m4 (v1, vl);
- vint32m4_t vw2 = __riscv_vsext_vf4_i32m4 (v2, vl);
- vint32m4_t vw3 = __riscv_vsext_vf4_i32m4 (v3, vl);
- vint32m4_t vw4 = __riscv_vsext_vf4_i32m4 (v4, vl);
- vint32m4_t vw5 = __riscv_vsext_vf4_i32m4 (v5, vl);
- vint32m4_t vw6 = __riscv_vsext_vf4_i32m4 (v6, vl);
- vint32m4_t vw7 = __riscv_vsext_vf4_i32m4 (v7, vl);
-
- asm volatile("nop" ::: "memory");
- size_t sum0 = __riscv_vmv_x_s_i32m4_i32 (vw0);
- size_t sum1 = __riscv_vmv_x_s_i32m4_i32 (vw1);
- size_t sum2 = __riscv_vmv_x_s_i32m4_i32 (vw2);
- size_t sum3 = __riscv_vmv_x_s_i32m4_i32 (vw3);
- size_t sum4 = __riscv_vmv_x_s_i32m4_i32 (vw4);
- size_t sum5 = __riscv_vmv_x_s_i32m4_i32 (vw5);
- size_t sum6 = __riscv_vmv_x_s_i32m4_i32 (vw6);
- size_t sum7 = __riscv_vmv_x_s_i32m4_i32 (vw7);
-
- sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7);
- }
- return sum;
-}
-
-/* { dg-final { scan-assembler-not {vmv1r} } } */
-/* { dg-final { scan-assembler-not {vmv2r} } } */
-/* { dg-final { scan-assembler-not {vmv4r} } } */
-/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
deleted file mode 100644
index 9b60005344d..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
-
-#include "riscv_vector.h"
-
-size_t __attribute__ ((noinline))
-sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3)
-{
- return sum0 + sum1 + sum2 + sum3;
-}
-
-size_t
-foo (char const *buf, size_t len)
-{
- size_t sum = 0;
- size_t vl = __riscv_vsetvlmax_e8m8 ();
- size_t step = vl * 4;
- const char *it = buf, *end = buf + len;
- for (; it + step <= end;)
- {
- vint8m2_t v0 = __riscv_vle8_v_i8m2 ((void *) it, vl);
- it += vl;
- vint8m2_t v1 = __riscv_vle8_v_i8m2 ((void *) it, vl);
- it += vl;
- vint8m2_t v2 = __riscv_vle8_v_i8m2 ((void *) it, vl);
- it += vl;
- vint8m2_t v3 = __riscv_vle8_v_i8m2 ((void *) it, vl);
- it += vl;
-
- asm volatile("nop" ::: "memory");
- vint32m8_t vw0 = __riscv_vsext_vf4_i32m8 (v0, vl);
- vint32m8_t vw1 = __riscv_vsext_vf4_i32m8 (v1, vl);
- vint32m8_t vw2 = __riscv_vsext_vf4_i32m8 (v2, vl);
- vint32m8_t vw3 = __riscv_vsext_vf4_i32m8 (v3, vl);
-
- asm volatile("nop" ::: "memory");
- size_t sum0 = __riscv_vmv_x_s_i32m8_i32 (vw0);
- size_t sum1 = __riscv_vmv_x_s_i32m8_i32 (vw1);
- size_t sum2 = __riscv_vmv_x_s_i32m8_i32 (vw2);
- size_t sum3 = __riscv_vmv_x_s_i32m8_i32 (vw3);
-
- sum += sumation (sum0, sum1, sum2, sum3);
- }
- return sum;
-}
-
-/* { dg-final { scan-assembler-not {vmv1r} } } */
-/* { dg-final { scan-assembler-not {vmv2r} } } */
-/* { dg-final { scan-assembler-not {vmv4r} } } */
-/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c
deleted file mode 100644
index dd65b2fa098..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
-
-#include "riscv_vector.h"
-
-size_t __attribute__ ((noinline))
-sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3)
-{
- return sum0 + sum1 + sum2 + sum3;
-}
-
-size_t
-foo (char const *buf, size_t len)
-{
- size_t sum = 0;
- size_t vl = __riscv_vsetvlmax_e8m8 ();
- size_t step = vl * 4;
- const char *it = buf, *end = buf + len;
- for (; it + step <= end;)
- {
- vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
- vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
- vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
- vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl);
- it += vl;
-
- asm volatile("nop" ::: "memory");
- vint64m8_t vw0 = __riscv_vsext_vf8_i64m8 (v0, vl);
- vint64m8_t vw1 = __riscv_vsext_vf8_i64m8 (v1, vl);
- vint64m8_t vw2 = __riscv_vsext_vf8_i64m8 (v2, vl);
- vint64m8_t vw3 = __riscv_vsext_vf8_i64m8 (v3, vl);
-
- asm volatile("nop" ::: "memory");
- size_t sum0 = __riscv_vmv_x_s_i64m8_i64 (vw0);
- size_t sum1 = __riscv_vmv_x_s_i64m8_i64 (vw1);
- size_t sum2 = __riscv_vmv_x_s_i64m8_i64 (vw2);
- size_t sum3 = __riscv_vmv_x_s_i64m8_i64 (vw3);
-
- sum += sumation (sum0, sum1, sum2, sum3);
- }
- return sum;
-}
-
-/* { dg-final { scan-assembler-not {vmv1r} } } */
-/* { dg-final { scan-assembler-not {vmv2r} } } */
-/* { dg-final { scan-assembler-not {vmv4r} } } */
-/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} } } */
