[gcc r15-102] s390: testsuite: Fix risbg-ll-2.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:66f49ccd409c7a3f6eb89dd78e275ab57c983c79

commit r15-102-g66f49ccd409c7a3f6eb89dd78e275ab57c983c79
Author: Stefan Schulze Frielinghaus <stefa...@linux.ibm.com>
Date:   Thu May 2 08:43:50 2024 +0200

    s390: testsuite: Fix risbg-ll-2.c
    
    Starting with r14-2047-gd0e891406b16dc we see through subregs which
    means for f10 in risbg-ll-2.c we do not end up with rosbg_si_noshift but
    rather rosbg_di_noshift which materializes in slightly different start
    index.  This saves us an extend.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/s390/risbg-ll-2.c: Fix start offset for rosbg of
            f10.

Diff:
---
 gcc/testsuite/gcc.target/s390/risbg-ll-2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c 
b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
index 8bf1a0ff88b..ca80602a83f 100644
--- a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
+++ b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
@@ -113,7 +113,7 @@ i32 f9 (i64 v_x, i32 v_y)
 // ands with incompatible masks.
 i32 f10 (i64 v_x, i32 v_y)
 {
-  /* { dg-final { scan-assembler 
"f10:\n\tsrlg\t%r2,%r2,48\n\trosbg\t%r2,%r3,32,39,0" { target { lp64 } } } } */
+  /* { dg-final { scan-assembler 
"f10:\n\tsrlg\t%r2,%r2,48\n\trosbg\t%r2,%r3,0,39,0" { target { lp64 } } } } */
   /* { dg-final { scan-assembler 
"f10:\n\tnilf\t%r4,4278190080\n\trosbg\t%r4,%r2,48,63,48" { target { ! lp64 } } 
} } */
   i64 v_shr6 = ((ui64)v_x) >> 48;
   i32 v_conv = (ui32)v_shr6;