https://gcc.gnu.org/g:fb7e62663cd40d434bbd2ae53082ca3f56ef2ef7
commit fb7e62663cd40d434bbd2ae53082ca3f56ef2ef7
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Mon May 20 14:25:40 2024 -0400
Add -mintspr
2024-05-20 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mintspr.
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Restrict
modes that go in SPRs to modes that fit in the SPR and are not
complex
modes. If -mintspr, restrict modes that go into SPRs to be scalar
integers.
(rs6000_opt_masks): Add -mintspr.
* config/rs6000/rs6000 (-mintspr): New option.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 1 +
gcc/config/rs6000/rs6000.cc | 27 ++++++++++++++++++++++++++-
gcc/config/rs6000/rs6000.opt | 4 ++++
3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index d625dbeb91fd..6fcbcbdadef7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -133,6 +133,7 @@
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
+ | OPTION_MASK_INTSPR \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
| OPTION_MASK_MMA \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 96241c18b617..7d5b94cda101 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1851,9 +1851,13 @@ static int
rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
+ bool orig_complex_p = false;
if (COMPLEX_MODE_P (mode))
- mode = GET_MODE_INNER (mode);
+ {
+ mode = GET_MODE_INNER (mode);
+ orig_complex_p = true;
+ }
/* Vector pair modes need even/odd VSX register pairs. Only allow vector
registers. */
@@ -1935,6 +1939,26 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if (CA_REGNO_P (regno))
return mode == Pmode || mode == SImode;
+ /* Possibly restrict SPR registers to have small scalar integers. */
+ switch (regno)
+ {
+ case VRSAVE_REGNO:
+ case VSCR_REGNO:
+ case LR_REGNO:
+ case CTR_REGNO:
+ {
+ unsigned reg_size = ((regno == VRSAVE_REGNO || regno == VSCR_REGNO)
+ ? 4
+ : UNITS_PER_WORD);
+
+ return (!orig_complex_p && GET_MODE_SIZE (mode) <= reg_size
+ && (!TARGET_INTSPR || SCALAR_INT_MODE_P (mode)));
+ }
+
+ default:
+ break;
+ }
+
/* AltiVec only in AldyVec registers. */
if (ALTIVEC_REGNO_P (regno))
return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
@@ -24463,6 +24487,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "power11", OPTION_MASK_POWER11, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false,
true },
{ "htm", OPTION_MASK_HTM, false, true },
+ { "intspr", OPTION_MASK_INTSPR, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 70fd7080bc52..2f3970b664cc 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -630,6 +630,10 @@ mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.
+mintspr
+Target Undocumented Mask(INTSPR) Var(rs6000_isa_flags)
+Disallow (allow) non-integer types in SPR registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
