[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] DSE: Fix ICE after allow vector type in get_stored_val

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:98a48906bfb653d1e18323997d0854bef18986e7

commit 98a48906bfb653d1e18323997d0854bef18986e7
Author: Pan Li <pan2...@intel.com>
Date:   Tue Apr 30 09:42:39 2024 +0800

    DSE: Fix ICE after allow vector type in get_stored_val
    
    We allowed vector type for get_stored_val when read is less than or
    equal to store in previous.  Unfortunately,  the valididate_subreg
    treats the vector type's size is less than vector register as
    invalid.  Then we will have ICE here.
    
    This patch would like to fix it by filter-out the invalid type size,
    and make sure the subreg is valid for both the read_mode and store_mode
    before perform the real gen_lowpart.
    
    The below test suites are passed for this patch:
    
    * The x86 bootstrap test.
    * The x86 regression test.
    * The riscv rv64gcv regression test.
    * The riscv rv64gc regression test.
    * The aarch64 regression test.
    
    gcc/ChangeLog:
    
            * dse.cc (get_stored_val): Make sure read_mode/write_mode
            is valid subreg before gen_lowpart.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/bug-6.c: New test.
    
    Signed-off-by: Pan Li <pan2...@intel.com>
    (cherry picked from commit 88b3f83238087cbe2aa2c51c6054796856f2fb94)

Diff:
---
 gcc/dse.cc                                      |  4 +++-
 gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c | 22 ++++++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/gcc/dse.cc b/gcc/dse.cc
index edc7a1dfecf..1596da91da0 100644
--- a/gcc/dse.cc
+++ b/gcc/dse.cc
@@ -1946,7 +1946,9 @@ get_stored_val (store_info *store_info, machine_mode 
read_mode,
                                 copy_rtx (store_info->const_rhs));
   else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode)
     && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_mode))
-    && targetm.modes_tieable_p (read_mode, store_mode))
+    && targetm.modes_tieable_p (read_mode, store_mode)
+    && validate_subreg (read_mode, store_mode, copy_rtx (store_info->rhs),
+                       subreg_lowpart_offset (read_mode, store_mode)))
     read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs));
   else
     read_reg = extract_low_bits (read_mode, store_mode,
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c
new file mode 100644
index 00000000000..5bb00b8f587
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c
@@ -0,0 +1,22 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize" } */
+
+struct A { float x, y; };
+struct B { struct A u; };
+
+extern void bar (struct A *);
+
+float
+f3 (struct B *x, int y)
+{
+  struct A p = {1.0f, 2.0f};
+  struct A *q = &x[y].u;
+
+  __builtin_memcpy (&q->x, &p.x, sizeof (float));
+  __builtin_memcpy (&q->y, &p.y, sizeof (float));
+
+  bar (&p);
+
+  return x[y].u.x + x[y].u.y;
+}