https://gcc.gnu.org/g:0ac802064c2a018cf166c37841697e867de65a95
commit r15-943-g0ac802064c2a018cf166c37841697e867de65a95
Author: Uros Bizjak <ubiz...@gmail.com>
Date: Fri May 31 15:52:03 2024 +0200
alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]
any_divmod instructions are modelled with invalid RTX:
[(set (match_operand:DI 0 "register_operand" "=c")
(sign_extend:DI (match_operator:SI 3 "divmod_operator"
[(match_operand:DI 1 "register_operand" "a")
(match_operand:DI 2 "register_operand" "b")])))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
where SImode divmod_operator (div,mod,udiv,umod) has DImode operands.
Wrap input operand with truncate:SI to make machine modes consistent.
PR target/115297
gcc/ChangeLog:
* config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode
operands 3 and 4 with truncate:SI RTX.
(*divmodsi_internal_er): Ditto for operands 1 and 2.
(*divmodsi_internal_er_1): Ditto.
(*divmodsi_internal): Ditto.
* config/alpha/constraints.md ("b"): Correct register
number in the description.
gcc/testsuite/ChangeLog:
* gcc.target/alpha/pr115297.c: New test.
Diff:
---
gcc/config/alpha/alpha.md | 21 ++++++++++++---------
gcc/config/alpha/constraints.md | 2 +-
gcc/testsuite/gcc.target/alpha/pr115297.c | 13 +++++++++++++
3 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 79f12c53c16..1e2de5a4d15 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -725,7 +725,8 @@
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand")))
(parallel [(set (match_dup 5)
(sign_extend:DI
- (any_divmod:SI (match_dup 3) (match_dup 4))))
+ (any_divmod:SI (truncate:SI (match_dup 3))
+ (truncate:SI (match_dup 4)))))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])
(set (match_operand:SI 0 "nonimmediate_operand")
@@ -751,9 +752,10 @@
(define_insn_and_split "*divmodsi_internal_er"
[(set (match_operand:DI 0 "register_operand" "=c")
- (sign_extend:DI (match_operator:SI 3 "divmod_operator"
- [(match_operand:DI 1 "register_operand" "a")
- (match_operand:DI 2 "register_operand" "b")])))
+ (sign_extend:DI
+ (match_operator:SI 3 "divmod_operator"
+ [(truncate:SI (match_operand:DI 1 "register_operand" "a"))
+ (truncate:SI (match_operand:DI 2 "register_operand" "b"))])))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
@@ -795,8 +797,8 @@
(define_insn "*divmodsi_internal_er_1"
[(set (match_operand:DI 0 "register_operand" "=c")
(sign_extend:DI (match_operator:SI 3 "divmod_operator"
- [(match_operand:DI 1 "register_operand" "a")
- (match_operand:DI 2 "register_operand" "b")])))
+ [(truncate:SI (match_operand:DI 1 "register_operand" "a"))
+ (truncate:SI (match_operand:DI 2 "register_operand" "b"))])))
(use (match_operand:DI 4 "register_operand" "c"))
(use (match_operand 5 "const_int_operand"))
(clobber (reg:DI 23))
@@ -808,9 +810,10 @@
(define_insn "*divmodsi_internal"
[(set (match_operand:DI 0 "register_operand" "=c")
- (sign_extend:DI (match_operator:SI 3 "divmod_operator"
- [(match_operand:DI 1 "register_operand" "a")
- (match_operand:DI 2 "register_operand" "b")])))
+ (sign_extend:DI
+ (match_operator:SI 3 "divmod_operator"
+ [(truncate:SI (match_operand:DI 1 "register_operand" "a"))
+ (truncate:SI (match_operand:DI 2 "register_operand" "b"))])))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_ABI_OSF"
diff --git a/gcc/config/alpha/constraints.md b/gcc/config/alpha/constraints.md
index 0d001ba26f1..4383f1fa895 100644
--- a/gcc/config/alpha/constraints.md
+++ b/gcc/config/alpha/constraints.md
@@ -27,7 +27,7 @@
"General register 24, input to division routine")
(define_register_constraint "b" "R25_REG"
- "General register 24, input to division routine")
+ "General register 25, input to division routine")
(define_register_constraint "c" "R27_REG"
"General register 27, function call address")
diff --git a/gcc/testsuite/gcc.target/alpha/pr115297.c
b/gcc/testsuite/gcc.target/alpha/pr115297.c
new file mode 100644
index 00000000000..4d5890ec8d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/alpha/pr115297.c
@@ -0,0 +1,13 @@
+/* PR target/115297 */
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+enum { BPF_F_USER_BUILD_ID } __bpf_get_stack_size;
+long __bpf_get_stack_flags, bpf_get_stack___trans_tmp_2;
+
+void bpf_get_stack() {
+ unsigned elem_size;
+ int err = elem_size = __bpf_get_stack_flags ?: sizeof(long);
+ if (__builtin_expect(__bpf_get_stack_size % elem_size, 0))
+ bpf_get_stack___trans_tmp_2 = err;
+}
